Packet Memory Controller Reader Listener Segmentation
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Solution Overview
Problem
In packet memory systems, broadcast and multicast traffic lead to performance issues due to simultaneous requests from multiple output ports, causing delays and underrun errors, especially in cut-thru mode where all ports transmit data as soon as possible without waiting for the entire packet to be received.
Innovation Solution
A packet memory system with a controller that designates a subset of reader ports to read packet data from the memory, allowing other ports to listen for the data without performing a read operation, thereby reducing contention and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all output ports read packet data simultaneously from packet memory, then each port can obtain data quickly, but the packet memory becomes overloaded causing underrun errors and performance degradation
Solution Approach 1:
The patent segments the set of output ports into two groups: reader ports that actually read packet data from packet memory, and listener ports that only listen to the data bus. This segmentation reduces the number of simultaneous read operations on packet memory, preventing overload and underrun errors while maintaining the ability to serve multiple output ports.
2Productivity
If multiple ports perform read operations simultaneously, then bandwidth utilization increases, but contention for packet memory access increases causing delays
Solution Approach 1:
The patent introduces an intermediary mechanism where reader ports act as intermediaries between packet memory and listener ports. Reader ports read data from packet memory and make it available on the data bus, allowing listener ports to obtain data without directly accessing packet memory. This intermediary approach increases bandwidth utilization while reducing access contention and delays.
3Reliability
If the system waits for entire packet reception before transmission, then data integrity is ensured, but transmission latency increases
Solution Approach 1:
The patent implements preliminary action by allowing output ports to begin transmitting packet data before the entire packet has been received from the network. The controller allocates packet memory space in advance and allows read operations to start as soon as enough data is available, reducing transmission latency while maintaining data integrity through proper buffer management.
Data Source
AI summary
A packet memory system for selectively outputting received packets on one or more output ports. The packet memory system including a controller for controlling the output ports. Specifically, for packets of multicast or broadcast traffic that needs to be output from a plurality of the ports, the controller designates one or more reader ports that read the packet data from a packet memory such that the remainder of the ports are able to simply listen for the read packet data without performing a read operation.