Packet Order Control Circuit Memory Optimization
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Solution Overview
Problem
Existing packet order control mechanisms, such as the DPDK reorder library, are not suitable for hardware implementation due to memory resource constraints and cannot guarantee packet processing order with limited memory resources, particularly in applications requiring high-speed network processing like image processing.
Innovation Solution
A packet order control technique that uses a hardware processing unit with a packet order control circuit, which includes a buffer, comparison circuit, and control circuit to selectively store and transfer packets based on packet IDs, allowing for accurate ordering without the need for multiple buffers, even in memory-restricted hardware environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DPDK reorder library is used to guarantee packet processing order, then packet order is ensured, but memory resources are excessively consumed due to requiring two buffers (order buffer and ready buffer)
Solution Approach 1:
The patent merges the order buffer and ready buffer into a single buffer structure. The buffer is divided into multiple storage areas, each corresponding to a different packet sequence number. This allows packets to be stored and retrieved in the correct order without requiring separate buffers, thereby reducing memory resource consumption while maintaining packet order guarantee.
Solution Approach 2:
The single buffer is segmented into multiple storage areas, where each area corresponds to a specific packet sequence number. This segmentation allows the system to track and retrieve packets in the correct order without needing multiple separate buffers, resolving the contradiction between memory efficiency and order guarantee.
2Reliability
If TCP protocol is used to guarantee packet processing order, then packet order is ensured, but processing delay increases due to complicated processing requirements
Solution Approach 1:
The patent extracts the packet ordering function from the transport layer protocol (TCP) and implements it directly in the data plane processing. By using a packet sequence number field in the packet header and maintaining a simple buffer structure with pointers, the system achieves packet ordering without the overhead of TCP's complicated processing, thereby reducing processing delay while maintaining order guarantee.
3Productivity
If hardware processing unit is used for high-speed network processing, then processing speed is improved, but memory resources are strictly restricted
Solution Approach 1:
The patent combines multiple buffer functions into a single buffer structure that can be implemented in hardware with limited memory resources. The buffer includes multiple storage areas indexed by packet sequence numbers, allowing efficient packet reordering without requiring the memory resources of traditional software-based solutions like DPDK.
Solution Approach 2:
The patent replaces software-based packet ordering mechanisms (which require extensive memory resources) with a hardware-based implementation using a simplified buffer structure and pointer management. This substitution enables high-speed network processing in hardware while consuming minimal memory resources.
Data Source
AI summary
A buffer (32) for temporarily storing a packet is installed in a packet order control circuit (12H). A comparison circuit (31) compares the packet ID of an input packet with a next-selection ID indicating the packet ID of a packet to be selected next in accordance with an order. If the comparison result indicates that the packet ID and the next-selection ID do not match, a control circuit (36) stores the input packet in a storage position corresponding to the packet ID. If the packet ID and the next-selection ID match, the control circuit (36) selects the input packet as a target of a transfer process without storing the packet in the buffer (32). If the next-selection ID matches the packet ID of a packet stored in the buffer (32), the control circuit (36) selects the packet as a target of the transfer process. This guarantees the packet processing order with few memory resources.