Packet Parser Sticky Transient Markers
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Solution Overview
Problem
Data networks face challenges in processing and forwarding large numbers of data packets efficiently, as general-purpose processors are not optimized for high-speed operations, leading to delays.
Innovation Solution
A packet parser and processor system that includes a rule processor and a plurality of marker elements, where the rule processor applies parsing rules to data packets and generates result address values to update selected marker elements, enabling efficient storage and processing of parsing results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If general-purpose processors are used to process data packets, then ease of operation is maintained, but processing speed and efficiency deteriorate
Solution Approach 1:
The processor is divided into specialized functional units including a rule processor for applying parsing rules, a marker unit with multiple marker elements for storing parsing results, and a packet processor for coordinating operations. Each unit handles specific tasks in the packet processing pipeline, enabling parallel operation and high-speed processing while maintaining manageable complexity through functional decomposition.
2Speed
If parsing results are stored in conventional memory structures, then storage capacity is sufficient, but access speed and efficiency deteriorate
Solution Approach 1:
The marker unit employs a multi-dimensional addressing structure where each marker element is identified by a result address value generated from parsing rules. This dimensional organization allows rapid direct access to parsing results based on rule outcomes, transforming the storage access pattern from sequential or hierarchical to direct and parallel, thereby significantly improving access speed.
3Productivity
If network processors operate at high speeds, then productivity improves, but processing accuracy and reliability may deteriorate
Solution Approach 1:
The rule processor generates result address values that directly index into the marker unit, creating a deterministic feedback loop between parsing operations and result storage. This structured feedback mechanism ensures that each parsing operation reliably maps to its corresponding result, maintaining accuracy while enabling high-speed parallel processing through predictable data flow patterns.
Data Source
AI summary
A packet parser has a set of marker elements each comprising a one bit latch and connected to store flag values from the results of the application of parser rules. Some marker elements are connected to provide the stored marker values as input to the parser rule logic to be taken into account in the processing of subsequent parser rules and some are connected to control external hardware. Some markers are reset at the end of each packet. A special toggle marker element toggles its value when its address is selected and other marker elements are connected to store, when its own address is selected, the value of the toggle element. Other markers toggle their own value when selected.