Automated Network Packet Pipeline Generation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The development of network packet processors is time-consuming and expensive due to the requirement of specialized knowledge from multiple fields of expertise, making rapid prototyping and iteration challenging.
Innovation Solution
A method is introduced to generate a pipeline for processing network packets by inputting a specification of packet processing actions, assigning these actions to stages, evaluating quality metrics, and selecting optimal assignments to create a pipeline that implements each action, allowing for efficient hardware implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hardware implementation of a network packet processor is developed using traditional methods requiring multiple fields of expertise, then the implementation quality and reliability are improved, but the development time and cost increase significantly
Solution Approach 1:
The patent introduces an automated code generation system that acts as an intermediary between protocol specifications and hardware implementation. This system automatically generates Verilog code from protocol specifications, eliminating the need for manual hardware design while ensuring implementation quality through systematic code generation.
Solution Approach 2:
The system enables self-service by automatically generating hardware implementation code from protocol specifications without requiring manual intervention from hardware designers. The automated generation process handles the complex translation from abstract protocol descriptions to concrete hardware code, reducing both time and expertise requirements.
2Manufacturing precision
If multiple fields of expertise are required for developing network packet processor hardware, then the technical quality is improved, but the complexity of the development process increases
Solution Approach 1:
The patent extracts the complex hardware design process from the protocol specification process. By separating these concerns and using automated code generation to bridge them, the system reduces development process complexity while maintaining technical quality through systematic code generation from verified protocol specifications.
3Productivity
If rapid development of network packet processors is achieved through automated code generation, then the development time is reduced, but the requirement for specialized expertise remains
Solution Approach 1:
The system creates accurate copies of protocol specifications in the form of Verilog hardware code through automated generation. This copying process maintains fidelity to the original protocol requirements while enabling rapid development, as the generated code can be directly synthesized into hardware implementations without manual translation.
Data Source
AI summary
Generating a pipeline for processing a type of network packets. A specification is input of the processing of the type of network packets. The specification specifies actions for inspecting and modifying one or more of the fields of the type of network packets. Assignments are generated that assign each of the actions to a corresponding stage of the pipeline. One or more of the actions is assigned to each stage of the pipeline. One or more quality metrics is evaluated for each of the assignments. A specific one of the assignments is selected in response to the quality metric or quality metrics. The pipeline is generated for the specific assignment. Each stage of the pipeline implements each action assigned to the stage.