Packet Processing Pipeline for NIC Policy Offload and Load Balancing

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Solution Overview

Problem

Data center operations face inefficiencies due to the use of CPU resources for network provisioning and storage, which could be better utilized for business logic and tenant hosting, and existing network interface devices lack efficient mechanisms for offloading packet processing operations.

Innovation Solution

Offload network policies and load balancing rules to a packet processing pipeline circuitry of a network interface device, which processes packets through a network policy table, recirculates the first packet to configure rules for the flow, and applies these rules to subsequent packets, thereby reducing CPU load and enhancing processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If CPU resources are used for network provisioning and storage operations, then networking and security functions can be performed, but CPU resources are consumed that could be used for business logic and tenant hosting

Engineering Contradiction:
Improvenetworking and security function performanceVSAvoidCPU resource availability for business logic
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts network provisioning, storage interface provisioning, load balancing, and security policy enforcement functions from the CPU to dedicated hardware components including network interface devices with programmable data planes and packet processing pipeline circuitry. This extraction allows CPU resources to be freed for business logic while maintaining networking and security functions through hardware-based processing.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If packet processing operations are handled by CPU, then network policies and load balancing can be applied, but processing efficiency is reduced due to CPU load

Engineering Contradiction:
Improvenetwork policy application accuracyVSAvoidpacket processing throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces packet processing pipeline circuitry as an intermediary between network interface devices and the CPU. This pipeline includes stages for parsing packets, checking network policies, performing load balancing, and enforcing security rules. The pipeline operates independently of the CPU, providing accurate network policy application while maintaining high packet processing throughput through hardware-based parallel processing.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If network interface devices use fixed-function data planes, then simple packet forwarding can be performed, but flexibility for complex network policies and load balancing is limited

Engineering Contradiction:
Improvepacket forwarding speedVSAvoidnetwork policy configuration flexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements programmable data planes in network interface devices that can be dynamically configured through a control plane. The data plane includes packet processing pipeline circuitry with multiple configurable stages that can be programmed to implement different network policies, load balancing algorithms, and security rules. This dynamic reconfigurability allows the system to adapt to changing requirements while maintaining high-speed hardware-based packet processing.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12489710B2Load balancing and networking policy performance by a packet processing pipeline
Publication Date: 2025.12.02 INTEL CORP
  • US12489710B2 patent drawing
  • US12489710B2 patent drawing
  • US12489710B2 patent drawing

AI summary

Examples described herein relate to a network interface device. In some examples, packet processing circuitry in the network interface device is to receive a first packet and based on the first packet being associated with an identifier for which an entry is not present in a look-up table accessible to the packet processing circuitry, the packet processing circuitry is to provide the identifier for the first packet and an action for the identifier of the first packet and cause the first packet to configure a second look-up-table accessible to the packet processing circuitry with the action for the identifier.