Packet Processing Power Consumption Measurement System
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Solution Overview
Problem
Integrated circuit (IC) manufacturers face challenges in early detection of power consumption issues and overheating during chip design verification, leading to significant wasted resources and increased costs due to the limitations of existing testing methods.
Innovation Solution
A system and method for obtaining power consumption data by sending test packets to a system under test (SUT) and receiving correlated power consumption data, using a test device with processors and communications interfaces to analyze and report power metrics, allowing for early identification of power-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If FPGA prototyping and conventional EDA tools are used for chip design testing, then testing can be performed prior to silicon fabrication, but power consumption issues and overheating problems cannot be detected early enough
Solution Approach 1:
The patent introduces a power consumption measurement intermediary that interfaces between the test device and the device under test. This intermediary captures power consumption data during packet processing tests and correlates it with test results, enabling early detection of power issues without requiring actual silicon fabrication. The intermediary acts as a bridge that translates physical power consumption into measurable data that can be analyzed during FPGA prototyping.
Solution Approach 2:
The patent replaces direct physical measurement of power consumption during FPGA operation with a computational model that simulates power consumption based on test packet processing. Instead of relying on physical power measurement hardware that would require silicon fabrication, the system uses software-based power consumption estimation that correlates test packet characteristics with expected power usage, enabling early detection during the FPGA prototyping phase.
2Reliability
If extensive testing and verification is performed on chip designs, then design reliability can be improved, but significant NRE costs are incurred
Solution Approach 1:
The patent performs preliminary power consumption analysis during FPGA prototyping before committing to silicon fabrication. By correlating test packet processing results with power consumption data in advance, the system identifies potential power-related reliability issues early in the design process, allowing corrections to be made during the reconfigurable FPGA phase rather than after expensive silicon fabrication. This preliminary action prevents wasted NRE costs on designs that would fail power consumption requirements.
Solution Approach 2:
The patent implements a feedback mechanism where power consumption measurement data from test packet processing is fed back into the design verification process. This feedback loop allows designers to iteratively refine chip designs based on actual power consumption observations during FPGA testing, improving design reliability through multiple cycles of testing and optimization before silicon fabrication, thereby reducing the need for expensive post-fabrication rework.
Data Source
AI summary
Methods, systems, and computer readable media for obtaining power consumption data associated with packet processing are disclosed. One method for obtaining power consumption data associated with packet processing occurs at a test device. The method includes sending, via a first communications interface, at least one test packet to a system under test (SUT). The method also includes receiving, via a second communications interface, power consumption data associated with the at least one test packet. The method further includes correlating the power consumption data and test packet information.