Packet Processing Array Topology Configuration via Dynamic Reconfiguration
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Solution Overview
Problem
Existing packet processing arrays with hard-wired topologies lack flexibility and increase manufacturing costs due to the need for different configurations, as they require extensive additional interfaces and complex physical layouts for reconfiguration.
Innovation Solution
A dynamically configurable packet processing array that uses a special topology configuration packet to reconfigure processing elements, allowing for flexible packet flow paths without additional hardware or interfaces, by distributing the packet through the array in the same manner as standard packets and utilizing multiplexers to select input packets based on configuration instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a hard-wired or fixed topology is used in packet processing arrays, then manufacturing precision and structural stability are improved, but adaptability and flexibility deteriorate
Solution Approach 1:
The patent implements dynamic reconfigurability by replacing fixed hard-wired connections with software-controlled virtual topology configuration. Processing elements can dynamically change their connection patterns and data flow paths through packet-based configuration protocols, allowing the same physical hardware to adapt to different processing requirements without physical reconfiguration.
Solution Approach 2:
The system changes the operational parameters of processing elements through virtual topology configuration packets. By modifying configuration parameters such as input/output port mappings, processing element activation states, and data flow routing instructions, the system achieves different topological configurations without changing the physical structure.
2Manufacturing precision
If hard-wired topologies are used for different configurations, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent creates a universal processing element design that can perform multiple functions through software configuration rather than requiring separate hard-wired configurations for each function. A single processing element can be reconfigured to handle different packet processing tasks by receiving appropriate configuration packets, eliminating the need for multiple specialized hardware variants.
Solution Approach 2:
The system uses virtual copying of topology configuration through packet transmission. Instead of physically duplicating hardware connections for different configurations, the configuration information is copied and transmitted as data packets to processing elements, which then replicate the desired connectivity pattern in the virtual switching fabric.
3Adaptability or versatility
If reconfiguration capabilities are added to packet processing arrays, then adaptability is improved, but device complexity and setup time increase
Solution Approach 1:
The patent replaces mechanical/physical reconfiguration mechanisms with electronic/software-based packet transmission. Instead of using physical switches, connectors, or mechanical reconfiguration hardware, the system uses data packets to convey topology configuration instructions, substituting a complex mechanical reconfiguration system with a simpler electronic communication approach.
4Manufacturing precision
If hard-wired topologies are used, then manufacturing precision is improved, but loss of time during configuration changes increases
Solution Approach 1:
The system performs preliminary configuration actions by pre-computing optimal topology configurations and encoding them into configuration packets before transmission. Processing elements receive pre-prepared configuration instructions that enable rapid reconfiguration without requiring real-time computation or complex negotiation during the actual reconfiguration event.
Data Source
AI summary
In some aspects, the disclosure is directed to methods and systems for topology configuration of an array of packet processing elements via a topology configuration packet. Each processing element may include input packet busses from a first plurality of neighboring processing elements and output packet busses to a second plurality of neighboring processing elements. Each processing element may receive the configuration packet from one of the first plurality of neighboring elements, set its own topology configuration register according to predetermined values within the packet, and forward the packet out all of its outputs, in the same manner as a standard packet.