Packet Processing Cache for NIC Latency Reduction
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Solution Overview
Problem
Network interface controllers face increased processing latency due to the high capacity queues required to manage large volumes of pending packet processing tasks, which are typically implemented in high-capacity memory devices, leading to slower access times and degraded network performance.
Innovation Solution
Implementing a cache memory system that prefetches and stores configuration data, such as memory descriptors, from these queues to provide faster access and ensure up-to-date information for packet processing tasks, using embedded SRAM for reduced latency and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high capacity memory devices are used to implement queues for buffering packet processing tasks, then the queue capacity increases to accommodate network speed and bandwidth, but the processing latency increases due to slower access times
Solution Approach 1:
The patent segments the queue implementation into two distinct memory components: a high-capacity memory device for buffering large volumes of packet processing tasks, and a separate cache memory device for storing frequently accessed configuration data. This segmentation allows each memory component to be optimized for its specific function, resolving the contradiction between queue capacity and access speed.
Solution Approach 2:
The cache memory device acts as an intermediary between the processor and the high-capacity memory device. It stores configuration data that would otherwise need to be repeatedly accessed from the slower high-capacity memory, thereby reducing processing latency without compromising queue capacity.
2Productivity
If high capacity memory devices are used to store queue information, then the network interface controller can handle increased packet volumes, but the access speed decreases leading to degraded performance
Solution Approach 1:
The patent applies local quality by providing different memory characteristics in different locations within the system. The cache memory device provides fast access locally for configuration data, while the high-capacity memory device provides large storage capacity remotely for queue buffering. This localized optimization resolves the contradiction between throughput and access speed.
Solution Approach 2:
The cache memory device pre-loads and stores configuration data that is likely to be needed for upcoming packet processing tasks. This preliminary action ensures that when packets need to be processed, the configuration data is already available in the fast cache memory, maintaining high processing speed and throughput.
Data Source
AI summary
A data or packet processing device such as a network interface controller may include cache control logic that is configured to obtain a set of memory descriptors associated with a queue from the memory. The set of descriptors can be stored in the cache. When a request for processing a data packet associated with the queue is received, the cache control logic can determine that the cache is storing memory descriptors for processing the data packet, and provide the memory descriptors used for processing the packet.