Packet Processing Circuit Clock Control for Power Reduction
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Solution Overview
Problem
Conventional packet processing circuits consume power continuously, even when no packets are being transmitted, leading to increased power costs and heat generation, and existing methods to reduce power consumption require additional control circuits.
Innovation Solution
A packet processing circuit with cascade-connected macros and a clock supply unit that stops clocking when no packet data is output for a predetermined time, using counter circuits to manage clock supply and minimize power consumption without increasing the number of control circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a gate signal is applied to clocks of a flip-flop for each word of data to validate clocks only when data changes, then power consumption is reduced, but the gating unit becomes small and the number of control circuits increases
Solution Approach 1:
The patent merges the clock control function with the packet processing function by using the packet data itself as the control signal. The clock signal is validated based on whether packet data is present, eliminating the need for separate gating circuits. This integration reduces the number of control circuits while maintaining power savings.
Solution Approach 2:
The packet data signal serves multiple functions: it is both the data to be processed and the control signal for clock validation. This multi-functionality eliminates the need for dedicated control circuits, as the same signal performs both data transmission and power management functions.
2Reliability
If a general packet processing circuit always receives clocks and consumes power independently of packet presence, then the circuit operates continuously and reliably, but power consumption increases during idle periods
Solution Approach 1:
The patent introduces dynamic clock control where the clock signal is activated or deactivated based on packet presence. The circuit transitions from a static continuous operation mode to a dynamic mode that adjusts its operation state according to actual packet processing needs, reducing power consumption during idle periods while maintaining reliability when packets are present.
Solution Approach 2:
The circuit operates periodically rather than continuously, with clock signals being supplied only during packet transmission periods. This periodic operation allows the circuit to maintain reliability during active periods while significantly reducing average power consumption during idle periods between packets.
Data Source
AI summary
A packet processing circuit includes a plurality of macros and a clock supply unit. Each of the macros processes packet data on the basis of a clock and outputs the processed packet data from at least one route. The macros are cascade-connected. The clock supply unit supplies the clock to a macro to be controlled and, when no packet data is output for a predetermined time from all routes of a macro on the input side of the macro to be controlled, stops supplying the clock to the macro to be controlled.