Packet Processing Clock Gating for Lower Peak Power
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Solution Overview
Problem
Current power-saving techniques for packet-processing devices in datacenters, such as network switches and routers, face limitations in reducing power consumption while maintaining performance, as they often require complex designs, increased latency, and redundant clock gating mechanisms that are not granular enough to address peak power reduction effectively.
Innovation Solution
The implementation of single-level inferred clock (SLICK) gating, which eliminates redundant clock gates and uses flow-aware clock-gating technology (FACT) to control flops with granular enables, allowing for efficient power savings without requiring long inactivity patterns, and the Continuously Variable Traffic (CVT) scheme to dynamically control active events and packet rates, reducing phantom activity and combinational toggle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If PSG (per-stage clock gating) is used to save power, then power consumption is reduced, but clock-gating efficiency decreases and chip area increases due to redundant clock gates
Solution Approach 1:
The patent extracts and removes the redundant SIG (synthesis-inferred clock gating) clock gate from the system, keeping only the necessary PSG (per-stage clock gating) clock gate. This elimination of redundant components directly improves clock-gating efficiency while maintaining power-saving functionality, resolving the contradiction between power reduction and device complexity.
2Loss of energy
If clock frequency is reduced to save power, then power consumption decreases, but latency increases and performance is degraded
Solution Approach 1:
The patent implements dynamic clock gating control where clock signals are selectively enabled or disabled based on actual traffic patterns and processing needs. This dynamic approach allows the system to maintain high clock frequencies when performance is needed while reducing frequencies only when idle, thereby reducing power consumption without incurring permanent latency penalties.
Solution Approach 2:
The patent employs periodic clock gating activation where clock signals are pulsed only during active processing periods rather than running continuously. This periodic action allows the system to save power during idle cycles while maintaining full performance capability when traffic arrives, effectively resolving the contradiction between power saving and latency.
3Loss of energy
If multiple levels of clock gating are implemented after H-tree tap, then power saving coverage is increased, but design complexity increases and tool compatibility decreases
Solution Approach 1:
The patent removes unnecessary multiple levels of clock gating and retains only the essential single level of PSG clock gating. This extraction of redundant complexity maintains adequate power-saving coverage while significantly simplifying the design and improving tool compatibility, resolving the contradiction between power saving coverage and design complexity.
4Reliability
If PSG activates clock for entire stage latency, then all flops are covered, but power saving is reduced when inactivity periods are shorter than stage latency
Solution Approach 1:
The patent applies partial clock gating activation where the clock is enabled only for the necessary portion of the stage latency rather than the entire duration. By activating the clock only when actually needed for processing and keeping it gated during idle periods within the stage, the system maintains reliable flops coverage while improving power-saving effectiveness even when inactivity periods are shorter than full stage latency.
Data Source
AI summary
A method for power-smart packet processing includes, in response to an event trigger signal, generating, by a state machine, a number of enable signals. The method further includes applying the enable signals to a number of single-level inferred clock (SLICK) gates to generate multiple clock signals with cycles of latency. The clock signals are applied to at least some of a number of groups of flops used for packet processing. The enable signals are clock-gated enable signals that start at consecutive cycles of a main clock, and stay active for at least one cycle of the main clock. The method further includes using flow-aware clock-gating technology (FACT) to distinctly identify logic and tables and continually variable traffic (CVT) to control packet rate and packet spacing.