Packet Processing System Dedicated Head Decoupling

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Solution Overview

Problem

Existing high-speed packet processing systems require significant CPU and memory resources and suffer from performance degradation due to sequential processing and unnecessary processes, especially in high-speed networks like 10 Gbps, where memory allocation and deallocation are necessary for each packet.

Innovation Solution

A high-speed packet processing system that pre-allocates data buffers and uses a dedicated head decoupled from these buffers to store packets sequentially, allowing simultaneous processing of multiple packets with minimized CPU and memory usage by employing the NAPI method, which reduces resource consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory is allocated or freed for every received packet in existing operating systems, then packet processing can be performed, but CPU and memory resources are significantly consumed and processing speed decreases

Engineering Contradiction:

Improvepacket processing speedVSAvoidCPU and memory resource consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent pre-allocates data buffers in advance before packet processing begins. These pre-allocated buffers are stored in a buffer pool that can be quickly assigned to incoming packets without requiring dynamic memory allocation, thereby eliminating the overhead of malloc/free operations and reducing CPU consumption.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent creates a single dedicated head (skb) that is decoupled from data buffers and can be reused across multiple packets. This single head structure serves multiple packets sequentially, eliminating the need to create and destroy separate memory structures for each packet, thus reducing both CPU overhead and memory allocation frequency.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If packets are processed sequentially in existing operating systems, then processing can be completed, but large amounts of CPU time and memory resources are required

Engineering Contradiction:

Improvepacket processing throughputVSAvoidCPU time consumption

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent segments the packet processing function into two independent parts: a reusable single dedicated head (skb) and pre-allocated data buffers. This segmentation allows the head to be reused across multiple packets while buffers are pre-prepared in a pool, enabling faster sequential processing without repeated memory allocation overhead.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The packet processing system uses pre-allocated buffers and a reusable head structure that eliminate the need for CPU-intensive dynamic memory management. The system serves itself by having ready-to-use memory structures, reducing dependency on CPU resources for allocation and freeing operations during packet processing.

Inventive Principle:

Principle #25Self-service

3Productivity

If various unnecessary processes are involved in transmitting packets, then packet transmission can occur, but performance drastically lowers in high-speed networks

Engineering Contradiction:

Improvehigh-speed network performanceVSAvoidnumber of processing steps

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts and removes unnecessary memory allocation and freeing processes from the packet transmission path. By using pre-allocated buffers and a reusable single head, the system eliminates redundant operations that do not contribute to actual packet transmission, thereby simplifying the processing pipeline and improving performance in high-speed networks.

Inventive Principle:

Principle #2Taking out (Extraction)

4Productivity

If multiple data buffers are allocated for simultaneous packet processing, then processing efficiency improves, but memory requirements increase

Engineering Contradiction:

Improvesimultaneous packet processing capabilityVSAvoidmemory quantity required

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent pre-allocates a pool of data buffers in advance and stores them in memory. These pre-allocated buffers are ready for immediate use when packets arrive, allowing multiple packets to be processed simultaneously without requiring dynamic memory allocation during processing, thus balancing memory usage with processing efficiency.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10187330B2High-speed packet processing system and control method thereof

Publication Date: 2019.01.22 KOREA UNIV RES & BUSINESS FOUND

AI summary

A high-speed packet processing system and a method of controlling the system are disclosed. The high-speed packet processing system includes: a network interface card configured to receive or transmit packets; a memory which is accessible by an operating system, and which includes at least one or more data buffers and a single dedicated head (dedicated skb) decoupled from the data buffers, where the data buffers are pre-allocated in correspondence to the packets to allow storing of the packets, and the single dedicated head is connected to the data buffers sequentially in correspondence to the packets; and a packet processing unit configured to sequentially connect the single dedicated head with the data buffers and store the packets sequentially in the data buffers corresponding to reception (Rx) descriptors based on the reception (Rx) descriptors designated in correspondence to the packets, when the packets are received.