Packet Processing Hardware Rotate-Merge and Deposit-Field Instructions
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Solution Overview
Problem
High-performance switches face challenges in processing Ethernet packets efficiently due to limited time per packet, necessitating simple packet manipulation hardware that cannot be reused for multiple computations, and require capabilities beyond the OpenFlow standard for diverse packet manipulations.
Innovation Solution
The implementation of a deposit-field instruction that allows for arbitrary bit manipulation by extracting a field from any position in a source operand and depositing it into any position in a background operand, along with a byte-rotate-merge operation, which simplifies packet processing by reducing hardware complexity and enabling more generic bit operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If packet manipulation hardware is made simple to complete processing in a single clock cycle, then processing speed is improved, but manipulation capability is limited
Solution Approach 1:
The patent implements a universal packet manipulation hardware unit that can perform diverse operations including field extraction, rotation, masking, merging, and depositing. This single multi-functional unit replaces what would otherwise require multiple specialized hardware units, enabling the hardware to adapt to different manipulation requirements while maintaining simple architecture suitable for single-clock-cycle operation.
2Adaptability or versatility
If hardware is pipelined to perform multiple computations for a packet, then manipulation capability is improved, but hardware complexity increases
Solution Approach 1:
The patent segments packet manipulation into distinct operational phases (extract, rotate, mask, merge, deposit) that can be executed sequentially within a single clock cycle. Each phase is handled by a dedicated functional component within the unified hardware unit, allowing complex multi-step manipulations to be completed without requiring multi-cycle pipelining or increasing overall hardware complexity.
3Productivity
If multiple copies of packet processing hardware are created to handle high packet rates, then processing throughput is improved, but manufacturing cost increases
Solution Approach 1:
By creating a single multi-functional packet manipulation unit that can handle diverse operations, the patent reduces the number of hardware copies needed. The universal unit can be replicated fewer times compared to multiple specialized units, lowering manufacturing costs while maintaining the ability to handle high packet rates through efficient single-clock-cycle operation.
Data Source
AI summary
In an embodiment of the invention, a method of performing a byte-rotate-merge on computer hardware is discussed. Byte-rotating is performed on first and second source operands and are byte-rotated by first and second rotation constants respectively. The first byte-rotate output and the second byte-rotate output are merged. Bytes from the first byte-rotate output are output to a byte-rotate-merge output when control bits from a byte-mask are logical ones. Bytes from the second byte-rotate output are output to a byte-rotate-merge output when control bits from the byte-mask are logical zeros.