Packet Processing Device DMA Transfer Descriptor Offset
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Solution Overview
Problem
Existing packet processing systems face challenges in reducing the hardware scale required for restoring multiple original packets from combined data blocks while maintaining high reception performance, especially when using collective DMA transfer or collective writing methods.
Innovation Solution
A packet processing apparatus that includes a data combining unit to concatenate data blocks and a combination data transfer unit to DMA-transfer or write these blocks to a data memory, with information on the starting address of each piece of data written to a descriptor, allowing for reduced hardware requirements and improved reception performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If collective DMA transfer or collective writing methods are used to combine multiple packets into one data block, then reception performance is improved and processor load is reduced, but the hardware scale required for restoring multiple original packets from the combined data block increases
Solution Approach 1:
The patent segments the combined data block into multiple individual packet units by storing offset information in the descriptor that indicates the starting position of each original packet within the combined data block. This allows the restoration process to be divided into separate extraction operations for each packet, reducing the complexity of hardware required for restoration while maintaining the efficiency benefits of collective transfer.
2Productivity
If collective DMA transfer is used to transfer multiple packets as one data block, then the number of DMA transfer operations is reduced, but the buffer area required in data memory increases
Solution Approach 1:
The patent employs dynamic buffer management where the buffer area is allocated based on the actual size of the combined data block rather than a fixed maximum size. The descriptor structure dynamically records the actual offset and size information of each packet within the combined block, allowing the buffer to be efficiently utilized without excessive allocation, thus reducing the required buffer area while maintaining reduced DMA operation counts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the hardware scale needed for packet restoration and enhances reception performance by lightening the processing load on the processor and reducing power consumption, while also minimizing the buffer area required in the data memory.
Implementation Method 1
a combination data transfer unit configured to DMA-transfer the data block generated by the data combining unit to the data memory
Data Source
AI summary
A packet processing apparatus includes a packet processor that performs processing on a packet received from a communication line and outputs data that is a result of the processing, a data combiner that concatenates a plurality of pieces of data output from the packet processor to generate a data block, and a combination data transferor that DMA-transfers the data block generated by the data combiner to a data memory. The combination data transferor writes information on an address in the data memory of a beginning of an individual piece of data in the data block to a descriptor that is a data area on a predetermined memory.