Packet Processing Device for 5G RAN Output Delay Reduction

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Solution Overview

Problem

In centralized radio access networks, especially in 5G communication systems, output delay occurs due to competition between high-priority mobile front haul (MFH) packets and low-priority mobile back haul (MBH) packets, which existing priority control processing methods fail to adequately address, leading to delays exceeding desirable limits.

Innovation Solution

A packet processing device that employs an autonomous Time Aware Shaper (TAS) method, utilizing folding analysis to quickly and accurately detect the true periodicity of arriving packets, allowing for precise gate control to prioritize and manage MFH packets, thereby reducing output delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If priority control processing is implemented to suppress output delay of high-priority MFH packets, then output delay of MFH packets is reduced, but processing complexity and potential interference with low-priority packets increases

Engineering Contradiction:
Improveoutput delay of MFH packetsVSAvoidpriority control processing complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent segments packet processing into distinct priority levels (MFH high-priority and MBH low-priority packets) and implements separate handling mechanisms for each. The gate control unit divides the output queue into multiple priority queues and controls them independently through separate gates, allowing MFH packets to be transmitted without waiting for MBH packets while preventing interference between the two types of traffic.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary gate control by opening the high-priority gate before low-priority packets are fully processed. The control unit predicts when high-priority MFH packets will arrive and opens the corresponding gate in advance, allowing these packets to be transmitted immediately without waiting for low-priority packet processing to complete, thus suppressing output delay proactively.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If TSN TAS method is used to suppress output delay, then packet output delay is reduced, but system complexity and coordination requirements increase

Engineering Contradiction:
Improvepacket output delayVSAvoidTAS gate control system complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent implements self-service by enabling the packet processing device to autonomously detect packet arrival periodicity and adjust gate opening/closing timing without external control. The analysis unit continuously monitors packet arrival patterns, calculates periodicity, and automatically generates gate control instructions, eliminating the need for complex centralized scheduling and coordination between multiple switches.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent employs feedback mechanisms where the analysis unit continuously monitors actual packet arrival times and compares them with expected periodicity. Based on this feedback, the control unit dynamically adjusts gate opening/closing timing to match actual traffic patterns, optimizing output delay suppression while adapting to changing network conditions without manual reconfiguration.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If autonomous period detection is implemented to accurately estimate packet periodicity, then gate control precision is improved, but detection time and processing load increase

Engineering Contradiction:
Improvepacket periodicity detection accuracyVSAvoiddetection time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies partial action by analyzing packet periodicity using a sliding window that processes only the most recent N packet arrival times rather than examining all historical data. The analysis unit maintains a fixed-size buffer of recent packet arrival timestamps and calculates periodicity based on this partial sample, achieving sufficient accuracy for gate control while significantly reducing processing time and computational load compared to full historical analysis.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10645015B2Packet processing device, transmission apparatus, packet processing method, and storage medium
Publication Date: 2020.05.05 FUJITSU LTD
  • US10645015B2 patent drawing
  • US10645015B2 patent drawing
  • US10645015B2 patent drawing

AI summary

A packet processing device includes a memory; and a processor configured to acquire an amount of packets arriving in each first section length as a first sampling value, determine a plurality of temporary periods based on a multiple of the first section length, calculate, for each of the temporary periods, a statistical value obtained by quantifying a bias in the amount of packets arriving in each first section length based on the first sampling value, estimate the temporary period having a maximum statistical value as a neighborhood period, acquire an amount of packets arriving in each second section length as a second sampling value, determine a plurality of neighborhood temporary periods around the neighborhood period, calculate a statistical value for each neighborhood temporary period based on the second sampling value, and estimate the neighborhood temporary period having the maximum statistical value as a true period of the arriving packets.