Packet Processing Device for 5G Mobile Front Haul Delay Reduction
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Solution Overview
Problem
In 5G communication systems, the output delay in mobile front haul (MFH) lines due to competition with mobile back haul (MBH) packets is significant, exceeding the desired 100 microseconds, which is exacerbated by the priority control mechanism that suspends high-priority packet reading until low-priority packets are fully read, leading to increased latency.
Innovation Solution
A packet processing device that processes packets in time slots, using multiple memories to store packets by type and a processor to control gate opening and closing based on packet arrival patterns, identifying burst sections and adjusting transmission timing to prioritize high-priority MFH packets, thereby reducing output delay by managing gate states across the communication system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If priority control operation is used to output high-priority packets first, then output delay for high-priority packets is reduced, but processing time increases when low-priority packets are being read
Solution Approach 1:
The system performs preliminary actions by reading low-priority packets in advance during time slots when high-priority packets are not arriving, so that when high-priority packets need to be output, the low-priority packets are already prepared and can be quickly processed without suspending the high-priority packet reading operation
Solution Approach 2:
The system dynamically adjusts the reading strategy based on packet arrival patterns and queue states, switching between reading high-priority packets immediately when they arrive and reading low-priority packets in advance when appropriate, optimizing the balance between output delay reduction and processing efficiency
2Manufacturing precision
If gate opening and closing timing is adjusted across multiple levels, then transmission timing precision is improved, but system complexity increases
Solution Approach 1:
The system segments the transmission timing control into independent units at different hierarchical levels, allowing each level to adjust its gate timing independently based on local packet arrival patterns while maintaining coordination with higher levels, thus achieving precise timing without requiring complete system redesign
Solution Approach 2:
The system implements feedback mechanisms where packet switches monitor their own queue states and packet arrival patterns, automatically adjusting their gate timing to optimize transmission scheduling, reducing the need for complex centralized control while maintaining timing precision across multiple levels
Data Source
AI summary
A packet processing device includes a first unit, a second unit, and a switching unit. The first unit counts the number of arrived packets in a first period that is from the time slot present after a priority section up to the end of the initial time slot in the subsequently-arriving priority section. When the counted number of arrived packets is positive, the first unit determines that forward mismatch has occurred in an observation cycle. The second unit counts the number of arrived packets in a second period which is from the time slot present immediately after the priority section in the first period of time up to the end of the initial time slot of burst sections in the subsequently-arriving priority section. When the counted number of arrived packets is “0”, the second unit determines that backward mismatch has occurred in the observation cycle.