Packet Processing Framework Dynamic Pipeline Assembly
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Solution Overview
Problem
Current networking architectures are not configured to exploit the exponentially increasing number of logical cores in a computing system, resulting in inefficiencies due to a rigid monolithic network pipeline.
Innovation Solution
A processing framework that segments functional components of a conventional network device into processing nodes, associates each node with a logical core, and dynamically assembles a network pipeline for each packet based on its requirements, allowing for efficient resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a rigid monolithic network pipeline is used, then the architecture is simple and easy to implement, but the processing resources are wasted and efficiency decreases as the number of logical cores increases
Solution Approach 1:
The patent segments the monolithic network pipeline into multiple independent processing nodes (e.g., input queue, packet processing nodes, output queue). Each processing node can be independently assigned to different logical cores, enabling parallel processing while maintaining a modular and manageable architecture that resolves the contradiction between simplicity and efficiency.
Solution Approach 2:
The patent introduces dynamic pipeline assembly where processing nodes can be dynamically assigned to different logical cores based on packet processing requirements. This dynamic allocation allows the system to adapt to varying workloads and exploit multiple logical cores efficiently, transforming the static rigid pipeline into a flexible dynamic structure that improves productivity without permanent architectural complexity.
2Productivity
If all pipeline stages process every network packet sequentially, then the pipeline is simple to implement, but resource utilization decreases and processing time increases
Solution Approach 1:
The patent divides the packet processing function into separate processing nodes that can operate in parallel on different logical cores. Instead of sequential processing through all stages, packets can be processed by multiple nodes simultaneously, reducing processing time while increasing throughput.
Solution Approach 2:
The patent creates a universal processing node design that can perform multiple functions (input queuing, packet processing, output queuing) and be dynamically assigned to different logical cores. This multi-functionality allows any processing node to handle various packet processing tasks, enabling flexible parallel processing that improves throughput without increasing processing time.
3Adaptability or versatility
If processing nodes are statically assigned to logical cores, then the system is easy to manage, but adaptability to different packet processing requirements is reduced
Solution Approach 1:
The patent implements dynamic node assignment where processing nodes can be assigned to different logical cores based on packet processing requirements rather than static configuration. This dynamic approach provides adaptability to different packet types and processing needs while using a standardized node design that keeps management relatively simple.
Solution Approach 2:
The patent changes the assignment parameter from static to dynamic, allowing processing nodes to be reassigned to different logical cores based on workload requirements. This parameter change enables the system to adapt to varying packet processing requirements while maintaining a consistent node interface and management protocol.
Data Source
AI summary
Techniques are disclosed for improved data routing and forwarding by exploiting the increasing number of logical cores in a computing system. In certain embodiments, a network device comprising several network interfaces and logical cores is disclosed. The network device may also include a plurality of processing nodes, wherein each processing node includes instructions for processing network packets and is associated with a logical core. Furthermore, the network device may include control logic configured to receive a network packet at an interface, select a subset of processing nodes from the plurality of processing nodes for processing the network packet, based on contents of the network packet and the interface that the network packet was received at, and schedule processing of the network packet by the subset of the processing nodes on the respective logical cores associated with each of the subset of the processing nodes.