Packet Processing Device Gate Control for 5G Bandwidth
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Solution Overview
Problem
The Time Aware Shaper (TAS) in 5G mobile communication networks faces challenges in efficiently managing communication resources, leading to decreased bandwidth for non-priority packets due to prolonged gate closure periods and inability to catch up with short intervals between high-priority packet transmissions, resulting in reduced bandwidth for non-MFH communication.
Innovation Solution
A packet processing device with multiple priority packet storages, a distributer, timing setting unit, read controller, and gate controller that adjusts the output timing of high-priority packets to minimize gate closure periods, allowing for successive forwarding of non-priority packets and optimizing communication bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the TAS closes the gate to stop non-MFH packet output when MFH packets are transmitted, then the delay of MFH packets is suppressed, but the bandwidth for non-MFH communication decreases due to prolonged gate closure periods
Solution Approach 1:
The patent segments the packet processing into multiple independent storage units (first packet storage unit and second packet storage unit) with different read cycles. The first storage unit stores non-MFH packets and the second stores MFH packets, allowing independent control of each queue's read timing without requiring complete gate closure, thus reducing the impact on non-MFH bandwidth while maintaining MFH priority.
Solution Approach 2:
The patent implements dynamic read cycle control where the read cycles of different packet storage units are adjusted based on traffic conditions. The timing setting unit dynamically sets read cycles for each storage unit, allowing the system to adaptively balance between MFH priority delivery and non-MFH bandwidth utilization, preventing fixed gate closure from causing excessive bandwidth loss.
2Manufacturing precision
If the TAS sets margin periods before and after gate closure for each MFH packet, then the gate control is precise, but the period in which non-MFH packets cannot be output increases when MFH packet frequency is high
Solution Approach 1:
By segmenting packet storage into separate units with independent read cycles, the patent eliminates the need for margin periods between MFH packets. Each storage unit can be read at its own optimized cycle without requiring additional margin time, thus maintaining precise control while eliminating time loss for non-MFH packets.
Solution Approach 2:
The patent enables continuous reading of non-MFH packets from the first packet storage unit at regular intervals without interruption. The read cycles are set to continuously read non-MFH packets during periods when MFH packets are not being transmitted, eliminating dead time and ensuring continuous useful action for non-MFH communication.
3Reliability
If the gate is held closed during gap periods between MFH packets, then MFH packet priority is maintained, but the bandwidth for non-MFH communication decreases
Solution Approach 1:
The patent segments the output process into independent reading operations from different storage units. Non-MFH packets are read from the first storage unit and MFH packets from the second storage unit independently, allowing non-MFH packets to be transmitted during gap periods between MFH packets without compromising priority control.
Solution Approach 2:
Instead of completely blocking non-MFH packet output during MFH transmission periods, the patent applies partial action by allowing limited non-MFH packet transmission during gap periods and using different read cycles. This partial approach maintains MFH priority while providing sufficient bandwidth for non-MFH communication.
Data Source
AI summary
A packet processing device includes: a non-priority packet storage that stores the non-priority packet; a gate provided on an output side of the non-priority packet storage; plural priority packet storages that respectively store the priority packet; a distributer that guides a received priority packet to a priority packet storage corresponding to a delay time of a route through which the received priority packet is transmitted; a timing setting unit that sets different read cycles to respective priority packet storages; a read controller that reads priority packets from the plural priority packet storages according to the read cycles; and a gate controller that controls the gate according to the timings on which the read priority packets are output. When the read controller reads a first priority packet from one of the priority packet storages, the read controller reads a second priority packet from another priority packet storage.