Packet Processing Apparatus Dynamic Gate Scheduling for Latency
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Solution Overview
Problem
In 5G communication systems, dynamic changes in allocation patterns based on the time division duplex (TDD) scheme can lead to increased output latency of high-priority packets in the wired section, particularly when switching between uplink and downlink directions within the same subframe, which affects the transmission efficiency and bandwidth utilization.
Innovation Solution
A packet processing apparatus that dynamically adjusts gate states for high-priority and low-priority packets based on periodicity patterns, preferentially outputting high-priority packets during predetermined time slots and normal output during other times, even when the allocation pattern changes, to maintain low latency and efficient bandwidth use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dynamic allocation patterns are used to adapt to traffic changes, then adaptability is improved, but output latency of high-priority packets increases
Solution Approach 1:
The system performs preliminary identification of periodicity patterns in high-priority packet arrivals and pre-configures gate opening/closing schedules before the actual packet arrival. This allows the system to prepare the transmission path in advance, ensuring that high-priority packets can be transmitted immediately when they arrive, thus reducing output latency while maintaining adaptability to traffic patterns
Solution Approach 2:
The system dynamically adjusts gate schedules based on detected periodicity patterns of high-priority packet arrivals. By making the gate control dynamic rather than static, the system can adapt to changing traffic conditions while ensuring that high-priority packets always find the gate open for transmission, thereby resolving the contradiction between adaptability and low latency
2Loss of time
If preferential output of high-priority packets is implemented, then output latency of high-priority packets is reduced, but transmission opportunities for low-priority packets are reduced
Solution Approach 1:
The system implements periodic gate opening schedules that are synchronized with the detected periodicity patterns of high-priority packet arrivals. By opening the gate periodically at predetermined timings rather than continuously, the system ensures high-priority packets are transmitted with minimal latency while also guaranteeing regular transmission opportunities for low-priority packets during the closed periods, thus balancing latency reduction with overall throughput maintenance
Solution Approach 2:
The system applies different gate control strategies to different packet types based on their priority and periodicity characteristics. High-priority packets receive preferential treatment with gates opened at specific periodic intervals, while low-priority packets are transmitted during other periods. This localized quality differentiation allows the system to optimize for high-priority latency without completely starving low-priority traffic, maintaining overall system throughput
Data Source
AI summary
A packet processing apparatus includes a memory, a processor, a first gate, and a second gate. The memory stores a plurality of allocation patterns for allocating an upstream or downstream of a link direction for each subframe within a predetermined period. The processor obtains a periodicity pattern of a high-priority packet for each of time slots within the subframe. The first gate opens and closes, for each of the time slots within the subframe, output of the high-priority packet. The second gate opens and closes, for each of the time slots within the subframe, output of a low-priority packet. The processor sets gate states of the first gate and the second gate for a predetermined time slot within the subframe in the same link direction as the periodicity pattern to a priority state in which the high-priority packet is preferentially output according to the periodicity pattern.