Hardware-Accelerated Packet Processing Control
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Solution Overview
Problem
Data centers face reduced functionality due to hardware limitations in top-of-rack switches, such as limited memory and inflexibility, and software-defined networking (SDN) systems fail to leverage desirable characteristics of hardware switches, leading to suboptimal performance and energy efficiency.
Innovation Solution
A control device coordinates multiple data plane components to dynamically distribute packet streams between hardware and software components based on detected characteristics, offloading simple processing to hardware switches and complex processing to software data planes, while utilizing user-defined policies to enhance speed and reduce energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If packet processing is performed using hardware switches, then processing speed is improved, but flexibility and adaptability deteriorate
Solution Approach 1:
The patent segments packet processing into two distinct paths: hardware-accelerated processing for simple packets and software-based processing for complex packets. The hardware switch handles basic forwarding tasks while the software data plane handles complex processing requirements, allowing each component to operate in its optimal performance regime.
Solution Approach 2:
The system dynamically selects between hardware and software processing paths based on packet characteristics and current system state. The control device monitors processing requirements and adjusts the distribution of packet streams between hardware and software components in real-time, optimizing both speed and flexibility adaptively.
2Adaptability or versatility
If packet processing is performed using software-defined networking, then flexibility is improved, but processing speed deteriorates
Solution Approach 1:
The patent segments packet processing into two distinct paths: hardware-accelerated processing for simple packets and software-based processing for complex packets. The hardware switch handles basic forwarding tasks while the software data plane handles complex processing requirements, allowing each component to operate in its optimal performance regime.
Solution Approach 2:
The system applies partial hardware acceleration by offloading only the portions of packet processing that can be handled by hardware (simple forwarding tasks) while keeping complex processing in software. This partial action approach allows the system to gain speed benefits where applicable without sacrificing the flexibility needed for complex operations.
3Use of energy by moving object
If hardware switches are used for packet processing, then energy efficiency is improved, but functionality deteriorates
Solution Approach 1:
The patent segments packet processing into two distinct paths: hardware-accelerated processing for simple packets and software-based processing for complex packets. The hardware switch handles basic forwarding tasks while the software data plane handles complex processing requirements, allowing each component to operate in its optimal performance regime.
Solution Approach 2:
The control device acts as an intermediary that coordinates between hardware switches and software data plane components. It distributes packet streams appropriately based on processing requirements, enabling the system to leverage both hardware energy efficiency and software functionality through intelligent traffic steering.
4Productivity
If coordination between hardware switches and software data planes is implemented, then overall performance is improved, but system complexity increases
Solution Approach 1:
The patent merges hardware switching and software data plane processing into a unified coordinated system. The control device integrates multiple data plane components (hardware switches and software data planes) to work together as a single system, leveraging the strengths of both approaches while managing complexity through centralized coordination.
Data Source
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AI summary
Devices and techniques for hardware accelerated packet processing are described herein. A device can communicate with one or more hardware switches. The device can detect characteristics of a plurality of packet streams. The device may distribute the plurality of packet streams between the one or more hardware switches and software data plane components based on the detected characteristics of the plurality of packet streams, such that at least one packet stream is designated to be processed by the one or more hardware switches. Other embodiments are also described.