Packet Processing Integrated Circuit Design via Hardware Description Language
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Solution Overview
Problem
Current systems for designing and implementing packet processing products are inefficient, as they either strain processor resources, are expensive and slow due to the use of network processing units (NPUs), or are cost-ineffective due to the design of customized application-specific integrated circuits (ASICs, which often waste resources for limited functionality.
Innovation Solution
A system and method that allows users to create instructions for building packet processing integrated circuits using a user interface to define packet processing algorithms, comprising discrete blocks and connections, which are processed to generate a hardware description language for producing an integrated circuit, including Packet Processing Units (PPUs), Packet Modification Units (PMUs), and Decision and Forwarding Units (DFUs, with optional external memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If parsing, decision, and routing functions are implemented in software modules executed by the host processor and memory, then the system is flexible and easy to program, but processing large amounts of data in real time is slow and strains processor resources
Solution Approach 1:
The patent replaces software-based packet processing (mechanical system) with hardware-based packet processing using an integrated circuit. The packet processing functions are implemented in dedicated hardware logic circuits that can process packets in parallel at line rate, eliminating the bottleneck of software execution on general-purpose processors while maintaining configurability through programmable elements within the hardware architecture
Solution Approach 2:
The patent changes the fundamental parameter of implementation medium from software to hardware. By implementing packet processing logic in hardware circuits with parallel processing capabilities, the system achieves both high-speed data processing and configurability through programmable hardware elements, resolving the contradiction between processing speed and adaptability
2Adaptability or versatility
If a specialized microprocessor and associated hardware called a network processing unit (NPU) is used, then the system provides programmable interface for nearly any type of protocol functionality, but the NPU becomes expensive and slow due to the large amount of functionality it must handle
Solution Approach 1:
The patent segments the packet processing functionality into distinct hardware modules including packet parsing units, decision units, and routing units. Each module handles specific aspects of packet processing independently, allowing parallel operation and eliminating the bottleneck of a single general-purpose NPU. This segmentation enables high-speed processing while maintaining protocol versatility through modular design
Solution Approach 2:
The patent implements dynamic configurability in the hardware architecture through programmable elements that allow the hardware circuits to be reconfigured for different protocols and processing requirements. This dynamic aspect enables the system to adapt to various protocol functionalities while maintaining high-speed hardware-based processing, avoiding the limitations of static or overly-general NPU designs
3Productivity
If a customized application specific integrated circuit (ASIC) is designed, then the system achieves dedicated functionality, but large numbers of gates are wasted to achieve only limited functionality, making it not cost effective
Solution Approach 1:
The patent creates a universal packet processing platform that can handle multiple protocols and processing requirements through a common hardware architecture. The system uses configurable hardware modules that can be programmed to perform different packet processing functions, eliminating the need for separate ASICs for each protocol or application. This universality maximizes gate utilization while maintaining processing efficiency across diverse use cases
Solution Approach 2:
The patent introduces dynamic reconfigurability to the hardware architecture, allowing the same physical circuit to adapt its functionality based on programming. This dynamic aspect enables a single ASIC design to serve multiple purposes, maximizing the utilization of logic gates and reducing waste compared to static, purpose-built ASICs. The system achieves both efficiency and versatility through programmable hardware
Data Source
AI summary
A system and method for allowing a user to create instructions for building a packet processing integrated circuit. The system includes a user interface for allowing a user to define a desired packet processing algorithm (4) using a plurality of discrete packet processing blocks (22, 24, 28, 30), each of the blocks corresponding to a portion of the desired packet processing algorithm (4). The system allows the user to define connections (10) between the plurality of packet processing blocks (22, 24, 28, 30). The system processes a plurality of packet processing blocks (22, 24, 28, 30) and the connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing the desired packet processing algorithm (19). The list of instructions can be delivered to a customer (12), or the customer can receive an integrated circuit constructed using the list of instructions (19), or the customer can receive a NETLIST generated using said list of instructions (16). The plurality of packet processing blocks (22, 24, 28, 30) can include a Packet Processing Unit (PPU, PPUX) 22, a Packet Modification Unit (PMU) 28, and a Decision and Forwarding Unit (DFU) 30.