Packet Processing Device Control Method for Reducing Latency

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Solution Overview

Problem

Packet processing devices face increased manufacturing costs, power consumption, and processing time due to the addition of functions, which are typically addressed by using a combination of hardware and software processing units, but software processing is slower and increases processing time, especially during table searches.

Innovation Solution

A control method for a packet processing device that includes a first memory for packet identification information and a second memory for processing execution information, where a first processor identifies processing execution information and transmits processing specification information to a second processor for executing packet processing, reducing the processing time by minimizing software processing unit workload.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If functions are added to the packet processing device by software processing, then adaptability is improved, but processing time increases

Engineering Contradiction:

Improvefunction adaptabilityVSAvoidprocessing time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent divides packet processing into multiple stages: hardware processing unit performs initial packet reception and basic filtering, while software processing unit handles complex processing tasks. This segmentation allows the system to maintain high-speed hardware processing for simple packets while providing software-based adaptability for complex processing requirements.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The hardware processing unit performs preliminary packet processing including reception, basic validation, and classification before passing packets to the software processing unit. This preliminary action reduces the workload on the software unit and allows software to focus only on complex processing tasks, thereby reducing overall processing time while maintaining adaptability.

Inventive Principle:

Principle #10Preliminary action

2Speed

If dedicated hardware is provided for each function, then processing speed is improved, but manufacturing cost increases

Engineering Contradiction:

Improveprocessing speedVSAvoidmanufacturing cost

Core Design Contradiction:

SpeedVSEase of manufacture

Solution Approach 1:

The hardware processing unit is designed as a universal platform that can handle multiple packet processing functions through configurable processing logic. Instead of providing dedicated hardware for each function, the system uses a multi-functional hardware unit that can be dynamically configured to perform different processing tasks, thereby reducing manufacturing cost while maintaining processing speed.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces a control unit that acts as an intermediary between the hardware processing unit and software processing unit. This control unit manages task distribution, coordinates processing workflows, and enables the hardware unit to perform multiple functions through software-controlled configuration, eliminating the need for separate dedicated hardware for each function.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Speed

If dedicated hardware is provided for each function, then processing speed is improved, but power consumption increases

Engineering Contradiction:

Improveprocessing speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by stationary object

Solution Approach 1:

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically allocates processing tasks between hardware and software units based on packet characteristics and processing requirements. The control unit adjusts the operational state of the hardware processing unit, activating only the necessary processing functions for each packet, thereby reducing power consumption while maintaining high processing speed when needed.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS9847940B2Control method, packet processing device, and storage medium

Publication Date: 2017.12.19 FUJITSU LTD

AI summary

A control method executed by a packet processing device, the control method includes receiving, by a first processor, a received packet; identifying first processing execution information corresponding to the received packet, from among a plurality of first processing execution information, by referring to the first memory, based on packet identification information included in the received packet; and transmitting processing specification information included in the identified first processing execution information together with the received packet, to a second processor, when the processing specification information included in the identified first processing execution information specifies processing by the second processor; receiving, by the second processor, the processing specification information included in the identified first processing execution information and the received packet; and executing the processing for the received packet in accordance with second processing execution information specified by the received processing specification information, by referring to the plurality of second processing execution information.