Hardware Packet Processing for MAC RLC and PDCP Offload

Solution Overview

Problem

Existing wireless communication systems face significant processing overhead and power consumption due to computation-intensive tasks in the MAC, RLC, and PDCP layers, which are typically handled by software in a central processing unit, leading to delays and inefficient use of CPU and memory resources.

Innovation Solution

Implementing hardware acceleration circuits to perform MAC, RLC, and PDCP processes without memory access, utilizing dedicated hardware modules for each protocol layer to streamline data transfer and reduce latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If software processing in CPU is used for MAC, RLC, and PDCP layers, then flexibility and adaptability are maintained, but processing speed decreases and power consumption increases

Engineering Contradiction:

Improvepacket processing speedVSAvoidhardware circuitry complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent segments the packet processing function into two parts: a hardware acceleration circuit that performs MAC, RLC, and PDCP processing, and a CPU that handles other tasks. This segmentation allows the time-consuming protocol layer processing to be offloaded from the CPU to dedicated hardware, thereby improving packet processing speed while maintaining system flexibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a memory-mapped I/O interface as an intermediary between the hardware acceleration circuit and the CPU/memory system. This intermediary enables the hardware circuit to access memory and exchange data with the CPU without burdening the CPU with the actual protocol processing tasks, thus resolving the contradiction between processing speed and device complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Use of energy by moving object

If software processing in CPU is used for MAC, RLC, and PDCP layers, then system flexibility is maintained, but power consumption increases

Engineering Contradiction:

Improvepower consumptionVSAvoidhardware circuitry complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent segments the packet processing function into two parts: a hardware acceleration circuit that performs MAC, RLC, and PDCP processing, and a CPU that handles other tasks. This segmentation allows the time-consuming protocol layer processing to be offloaded from the CPU to dedicated hardware, thereby improving packet processing speed while maintaining system flexibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a memory-mapped I/O interface as an intermediary between the hardware acceleration circuit and the CPU/memory system. This intermediary enables the hardware circuit to access memory and exchange data with the CPU without burdening the CPU with the actual protocol processing tasks, thus resolving the contradiction between processing speed and device complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Speed

If hardware acceleration circuitry is used for MAC, RLC, and PDCP processes, then packet processing speed increases, but memory access requirements change

Engineering Contradiction:

Improvepacket processing speedVSAvoidmemory access operation

Core Design Contradiction:

SpeedVSEase of operation

Solution Approach 1:

The patent introduces a memory-mapped I/O interface as an intermediary between the hardware acceleration circuit and the CPU/memory system. This intermediary enables the hardware circuit to access memory and exchange data with the CPU without burdening the CPU with the actual protocol processing tasks, thus resolving the contradiction between processing speed and device complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The hardware acceleration circuit is designed to autonomously perform MAC, RLC, and PDCP processing tasks without requiring CPU intervention. The circuit independently manages its own operations, including receiving transport blocks from the physical layer, processing them through the protocol layers, and delivering resulting packets to upper layers, thereby simplifying memory access operations.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS20250380187A1Method and device for speeding up packet processing

Publication Date: 2025.12.11 MEDIATEK INC

AI summary

A method for speeding up packet processing is provided. The method includes receiving a downlink TB from a PHY layer. The method includes performing a MAC process on the downlink TB to obtain MAC SDUs. The method includes performing an RLC process on RLC PDUs corresponding to the MAC SDUs to obtain RLC SDUs. The method includes performing a PDCP process on PDCP PDUs corresponding to the RLC SDUs to obtain PDCP SDUs. The method includes determining whether each of the PDCP SDUs corresponding to a packet is an Internet protocol (IP) packet or a TCP/UDP packet. The method includes performing related processing on the packet to obtain a processed packet in response to determining that the packet is an IP packet or a TCP/UDP packet. The method includes transmitting the processed packet to an upper layer.