Packet Processing Apparatus with Periodic Queue Control for Mobile Fronthaul Delay
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Solution Overview
Problem
In communication systems employing the CPRI scheme for mobile fronthaul networks, high-priority MFH packets experience significant output delay due to conflicts with lower-priority packets, which is not adequately addressed by existing priority control processing methods, necessitating a more effective solution to reduce delay in multi-level node architectures.
Innovation Solution
A packet processing apparatus with multiple queues that identifies periodicity patterns in packet arrival times and controls the opening and closing of queues based on these patterns to prioritize high-priority MFH packets, allowing for preferential output without stopping the processing of lower-priority packets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If priority control processing is used to preferentially read high-priority packets, then output delay of high-priority packets is reduced, but a wait corresponding to up to approximately one packet occurs when a high-priority packet arrives while a low-priority packet is being read
Solution Approach 1:
The patent implements periodic gate opening/closing actions at predetermined intervals to allow high-priority packets to be read preferentially. By periodically opening gates for high-priority queues at specific time slots, the system ensures that high-priority packets can be transmitted without being blocked by low-priority packets, thereby reducing output delay while maintaining systematic processing efficiency.
2Loss of time
If TSN TAS scheme is used to reduce output delay of high-priority packets, then output delay is reduced, but complex adjustments and time synchronization are required across the entire communication system
Solution Approach 1:
The patent enables each packet switch to autonomously control its own queue gates based on locally stored gate control information, without requiring complex time synchronization or coordination with other switches in the system. Each switch independently determines when to open or close gates for high-priority queues, simplifying the overall system architecture while still achieving reduced output delay for high-priority packets.
3Loss of time
If gates are opened and closed to prioritize high-priority packet output, then output delay of high-priority packets is reduced, but packet transmission timing must be coordinated across multiple packet switches
Solution Approach 1:
The patent pre-calculates and stores gate control information in each packet switch before packets arrive. The gate opening/closing timings are determined in advance based on expected high-priority packet arrivals, allowing switches to automatically execute the predetermined gate control actions without real-time coordination or complex timing calculations during packet transmission.
Data Source
AI summary
A packet processing apparatus includes a plurality of queues that store received packets according to types of the received packets; and a processor coupled to the plurality of queues and configured to: collect information on packet quantity of received packets in each time slot, identify a periodicity pattern of the received packets based on the packet quantity of the received packets in each time slot, based on the identified periodicity pattern of the received packets, identify a time slot section where received packets of a predetermined type are to be outputted preferentially, and control opening and closing of each of the plurality of queues in the identified time slot section.