Packet Processor Header Routing for Low Latency
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Solution Overview
Problem
In high-bandwidth packet processing devices, the latency is increased due to the need for the header processor to wait for the entire packet header to be stored in packet memory before processing can begin, especially for short packets where most of the data is the header, leading to inefficiencies and potential packet drops.
Innovation Solution
The packet processor is designed to route the header directly to the header processor while the payload is loaded into packet memory, allowing processing to start as soon as the header is received, and implementing mechanisms such as an Early Header interface and configurable logical header length to reduce latency, along with optimizing queue management and data retrieval to prevent under-run conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the header processor waits for the entire packet header to be stored in packet memory before processing, then data integrity is ensured, but packet processing latency increases
Solution Approach 1:
The patent applies preliminary action by enabling the header processor to begin processing the packet header as soon as it is received from the receive direct memory access block, without waiting for the entire packet to be stored in packet memory. This allows processing to start in advance, reducing latency while maintaining data integrity through controlled access mechanisms.
Solution Approach 2:
The patent segments the packet into header and payload portions, allowing the header to be processed independently and in parallel while the payload is being stored. This segmentation enables the header processor to work on the header portion separately, reducing overall processing latency without compromising data integrity.
2Measurement precision
If the header processor waits for the header to be stored in packet memory, then processing accuracy is maintained, but processing speed decreases
Solution Approach 1:
The header processor performs processing actions preliminarily, starting as soon as the header data is available from the receive direct memory access block, rather than waiting for complete storage in packet memory. This preliminary processing maintains accuracy through controlled data access while significantly improving processing speed.
3Productivity
If the packet processor processes short packets where most data is header, then throughput is improved, but latency increases due to waiting for header storage
Solution Approach 1:
For short packets where the header constitutes most of the data, the patent applies preliminary action by enabling the header processor to start processing immediately when the header is received, without waiting for complete storage in packet memory. This reduces latency significantly for short packets while maintaining high throughput.
Solution Approach 2:
The patent applies partial action by processing only the header portion of the packet in advance, which is sufficient for making processing decisions. For short packets where the header is most of the data, this partial processing approach achieves near-complete processing without waiting for the entire packet to be stored, reducing latency while maintaining throughput.
Data Source
AI summary
A packet processor includes a header processor and a packet memory. A receive direct memory access block is configured to receive a packet with a header and a payload and to route the header to the header processor and to route the payload to the packet memory such that the header processor begins processing of the header while the payload is loaded into packet memory.