Packet Processor Memory Banks for Parallel Table Access

Solution Overview

Problem

Prior art packet processors face limitations in memory access efficiency, leading to delays and packet dropping due to the need for multiple separate accesses to retrieve table information for processing packets, especially during line rate processing of small packets.

Innovation Solution

A packet network processor memory system with multiple memory banks, each with separate address buses, allowing concurrent memory access and using a memory process configuration table to store access instructions for efficient retrieval of table entries, enabling simultaneous access to non-overlapping tables and reducing burst mode memory accesses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If multiple separate memory accesses are used to retrieve table information, then complete table entries can be retrieved, but memory access time increases and packet processing latency increases

Engineering Contradiction:

Improvememory access timeVSAvoidpacket delivery reliability

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

The memory system is divided into multiple independent memory banks (first memory bank, second memory bank, etc.), each capable of autonomous access. Table entries are segmented and stored across different banks, allowing parallel retrieval of multiple table entries simultaneously through separate address buses, thereby reducing total memory access time while maintaining complete information retrieval for packet processing

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple memory banks are combined into a unified memory system with a single address space. The system merges the capabilities of multiple independent memory units to provide both parallel access (reducing time) and complete data retrieval (ensuring reliability). The memory controller coordinates accesses across banks to deliver complete table entries needed for packet processing

Inventive Principle:

Principle #5Merging (Combining)

2Productivity

If multiple separate memory accesses are used to retrieve table information, then all required information can be obtained, but packet processing speed decreases

Engineering Contradiction:

Improvepacket processing speedVSAvoidmemory access time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The memory system is divided into multiple independent memory banks (first memory bank, second memory bank, etc.), each capable of autonomous access. Table entries are segmented and stored across different banks, allowing parallel retrieval of multiple table entries simultaneously through separate address buses, thereby reducing total memory access time while maintaining complete information retrieval for packet processing

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The memory banks operate continuously and independently, with each bank able to service memory requests without waiting for other banks. This continuous parallel operation eliminates idle time in the memory access pipeline, maintaining high packet processing speed by ensuring that memory retrieval operations proceed without unnecessary delays

Inventive Principle:

Principle #20Continuity of useful action

3Device complexity

If a single memory device is used, then the memory system is simple, but multiple separate accesses are required to retrieve table information

Engineering Contradiction:

Improvememory system complexityVSAvoidmemory access efficiency

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The memory system is divided into multiple independent memory banks (first memory bank, second memory bank, etc.), each capable of autonomous access. Table entries are segmented and stored across different banks, allowing parallel retrieval of multiple table entries simultaneously through separate address buses, thereby reducing total memory access time while maintaining complete information retrieval for packet processing

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Each memory bank is designed with universal functionality to handle any memory access request independently. All banks use the same address bus interface and can be accessed simultaneously without complex coordination logic, maintaining relative simplicity while achieving high access efficiency through parallel operations

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8599844B2System and method for flexible memory system configuration and access

Publication Date: 2013.12.03 DELL MARKETING CORP

AI summary

A packet network device includes a packet network processor memory system for storing information used to process and forward packets of information in and through the network device. The information is included in look-up tables whose entries can be mapped either horizontally or vertically into the memory system. In the event that the entries are mapped horizontally, a complete entry can be access at a single memory location and in the event that the entries are mapped vertically, the entries can be accessed at one or more memory locations.