Packet Processor Offloading Without IOMMU
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multiprocessor systems face latency and complexity issues during data and code transfer between processors due to the need for Input/Output Memory Management Units (IOMMUs), which increase silicon area and power dissipation, and require significant OS mediation and component burden.
Innovation Solution
The apparatus and method utilize a packet processor with a hardware address translator to manage communications between processors, allowing direct execution of computing kernels on co-processors without IOMMUs, using virtual address spaces and reducing the need for continuous physical memory allocation, enabling efficient kernel offloading and co-processor utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If IOMMUs are used to manage data and code transfer between processors, then memory management and address translation are improved, but silicon area and power dissipation increase
Solution Approach 1:
The patent extracts the address translation functionality from the traditional IOMMU and implements it directly within the packet processor using hardware address translators. This eliminates the need for separate IOMMU components while maintaining the essential memory management capabilities, thereby reducing silicon area without compromising reliability
Solution Approach 2:
The patent combines multiple functions including address translation, packet processing, and memory management into a single integrated packet processor. By merging these functions that were previously handled by separate components (IOMMU, DMA controllers, etc.), the system reduces overall silicon area while maintaining effective memory management between host CPU and co-processors
2Reliability
If IOMMUs are used to manage data and code transfer between processors, then memory management and address translation are improved, but power dissipation increases
Solution Approach 1:
The patent removes the power-consuming IOMMU component from the system architecture and replaces its functionality with more efficient hardware address translators embedded in the packet processor. This extraction eliminates unnecessary power dissipation while maintaining reliable memory management between processors
Solution Approach 2:
By merging address translation and memory management functions into the packet processor, the system eliminates the need for separate IOMMU power consumption. The integrated approach reduces overall power dissipation while maintaining effective memory management capabilities across the heterogeneous processing system
3Reliability
If IOMMUs and OS mediation are used for kernel offloading, then processor communication and memory mapping are improved, but system complexity and component burden increase
Solution Approach 1:
The patent extracts the address translation functionality from the IOMMU and places it directly in the packet processor. This eliminates the need for complex IOMMU-OS coordination and reduces system complexity while maintaining reliable processor communication and memory mapping for kernel offloading operations
Solution Approach 2:
The packet processor serves as an enhanced intermediary between the host CPU and co-processors, integrating address translation capabilities directly within itself. This eliminates the need for external IOMMUs and reduces OS mediation complexity, while maintaining reliable communication and memory mapping for kernel offloading
4Reliability
If continuous physical memory allocation is required for co-processor execution, then memory accessibility is improved, but memory management overhead and system complexity increase
Solution Approach 1:
The patent changes the memory address parameter representation by implementing hardware address translators that can directly translate virtual addresses to physical addresses within the packet processor. This eliminates the need for continuous physical memory allocation while maintaining memory accessibility, thereby reducing memory management overhead and system complexity
Data Source
AI summary
A method of offloading a computing kernel from a host central processing unit (CPU) to a co-processor includes obtaining, by an application running on the host CPU, a virtual address of a packet in a user level queue of a general packet processing unit (GPPU) and initializing, by the application, the packet referenced by the virtual address using an application programming interface of a user level device driver (ULDD). The packet includes a plurality of handles corresponding to the computing kernel. The method further includes finalizing, by the ULDD, the packet by including a list of bootstrap translation addresses comprising a physical address and a virtual address for each of the plurality of handles and output by a kernel level device driver (KLDD) of an operating system running on the host CPU, and accessing, by the application using the virtual address, results obtained from the co-processor processing the computing kernel.