Packet Processor Behavior Modeling via Petri Nets

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Solution Overview

Problem

The complexity of analyzing possible orders of execution in packet processors to enable parallel operations is hindered by exponential growth in the number of possible orders, making it time-consuming and difficult to implement efficient and high-performance processing.

Innovation Solution

A declarative description of packet processor rules is converted into a dependency graph and then a Petri net, which represents the behaviors of the processor, allowing for the identification of feasible orders of execution and parallel processing while adhering to implementation constraints.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of operations in the packet processor increases to enable more parallel processing, then the processing performance and efficiency are improved, but the complexity of analyzing possible orders of execution increases exponentially

Engineering Contradiction:
Improveprocessing performanceVSAvoidanalysis complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces Petri nets as an intermediary formalism to represent and analyze the execution orders of packet processor operations. Petri nets provide a graphical and mathematical framework that models concurrent processes, making it feasible to analyze complex parallel execution scenarios without facing exponential complexity. The Petri net representation allows systematic analysis of operation dependencies and parallel execution possibilities.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent transforms the problem representation from traditional analytical methods to Petri net parameters and structures. By changing the representation parameters (using places, transitions, and tokens in Petri nets), the patent enables efficient analysis of operation execution orders. This parameter transformation allows the system to handle increased numbers of operations without proportional increases in analysis complexity.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If more operations are performed in parallel to improve processing efficiency, then the throughput is increased, but the resource requirements and implementation difficulty increase

Engineering Contradiction:
ImprovethroughputVSAvoidimplementation difficulty
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by using Petri nets to analyze and determine optimal parallel execution orders before implementing the packet processor. By modeling all possible execution orders and dependencies in advance using Petri net formalism, the design process identifies feasible parallel configurations and resource requirements upfront, reducing implementation difficulty while maximizing throughput.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If traditional analytical methods are used to explore alternative implementations, then the analysis is thorough, but the time consumption and computational resources required increase exponentially

Engineering Contradiction:
Improveanalysis thoroughnessVSAvoidanalysis time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent substitutes traditional mechanical analytical methods with the mathematical framework of Petri nets. Instead of manually analyzing execution orders through conventional methods, the patent uses Petri net theory and algorithms to automatically explore and evaluate alternative implementations. This substitution maintains analysis thoroughness while dramatically reducing the time and computational resources required.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS8082527B1Representing the behaviors of a packet processor
Publication Date: 2011.12.20 XILINX INC
  • US8082527B1 patent drawing
  • US8082527B1 patent drawing
  • US8082527B1 patent drawing

AI summary

Methods are provided for compactly representing behaviors of a processor of packets. A declarative description of the processor is input. The declarative description specifies rules for manipulating the packets. A dependency graph is generated from the declarative description. The dependency graph specifies each rule that depends upon another one or more of the rules. The declarative description and the dependency graph are transformed into a Petri net representing the behaviors of the processor. The Petri net includes respective transitions for the rules and places for enabling the transitions to fire. A specification of the Petri net is output. The Petri net represents the behaviors of the processor.