Programmable Packet Processor Pipeline for Rapid Hardware Iteration
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Solution Overview
Problem
The development of network packet processors is time-consuming and expensive due to the requirement of specialized knowledge from multiple fields of expertise, making rapid prototyping and iteration challenging.
Innovation Solution
A packet processor with a programmable compute pipeline and memory that stores microcode specifying packet types, allowing for sequential processing and easy modification of packet processing actions, enabling quick generation and updating of hardware implementations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hardware implementation of a network packet processor is developed using specialized knowledge from multiple fields, then the processing reliability and performance are improved, but the development time and cost increase
Solution Approach 1:
The patent uses a parsing tree data structure that serves as a virtual model or copy of the packet processing logic. This parsing tree can be automatically converted into hardware implementation code, allowing multiple iterations of design and testing in the virtual domain before final hardware deployment, thereby reducing development time while maintaining reliability
Solution Approach 2:
The patent introduces an intermediate representation (parsing tree) that bridges the gap between protocol specification and hardware implementation. This intermediary structure allows automated code generation and simplifies the translation process, reducing both development time and the need for multiple specialized expertise areas
2Reliability
If a hardware implementation of a network packet processor is developed using specialized knowledge from multiple fields, then the processing quality is improved, but the development cost increases
Solution Approach 1:
The parsing tree serves as a reusable virtual model that can be automatically converted into hardware code. This copying approach allows the same design to be iterated and refined multiple times without additional hardware fabrication costs, improving quality while controlling development expenses
Solution Approach 2:
The system employs automated code generation that transforms the parsing tree into hardware implementation code without requiring manual intervention for each conversion. This self-service automation reduces labor costs and minimizes the need for multiple specialized engineers, thereby reducing overall development cost while maintaining high processing quality
3Reliability
If rapid iterations of hardware implementation are performed to address deficiencies, then the packet processor quality is improved, but the development time for each iteration increases
Solution Approach 1:
The parsing tree can be rapidly copied and modified to create new versions of the packet processor logic. Since the parsing tree is a virtual data structure rather than physical hardware, multiple iterations can be performed quickly by simply modifying the tree structure and regenerating code, thereby improving iteration speed without sacrificing quality
Solution Approach 2:
The system allows dynamic modification of the parsing tree structure to adapt to protocol changes or fix deficiencies. This dynamic approach enables rapid reconfiguration of the packet processing logic through software-level changes to the parsing tree, which can then be automatically converted to hardware code, significantly increasing iteration speed while maintaining quality improvements
Data Source
AI summary
A packet processor includes a memory and a programmable compute pipeline. The memory stores microcode that specifies respective sets for the packet types, and the respective set for each type specifies packet fields. The programmable compute pipeline includes a sequence of stages beginning with an initial stage. The initial stage includes an operand selector that extracts a data vector from each packet. The operand selector is programmable to extract the data vector that includes each field specified in the respective set for the type of each packet. Each stage except the initial stage inputs a first version of the data vector and each stage outputs a second version of the data vector. Each stage except the initial stage generates the second version of the data vector that replaces a part of the first version of the data vector with a result that the stage computes from the part.