Network Packet Processor Scheduling via Textual Specification
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Solution Overview
Problem
The development of network packet processors is time-consuming and requires expertise from multiple fields, making rapid prototyping and improvement challenging.
Innovation Solution
A method for scheduling a network packet processor using a textual language specification that includes memory read and modification actions, determining availability and storage classes for fields, and employing a look-ahead interval to generate a hardware description language specification for efficient hardware implementation in a programmable logic device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a hardware implementation of a network packet processor is developed using traditional methods requiring multiple fields of expertise, then the implementation can be customized and optimized, but the development time and cost increase significantly
Solution Approach 1:
The patent uses template-based hardware generation where pre-defined hardware modules and configurations are copied and assembled automatically from protocol specifications. This allows rapid replication of proven hardware designs without requiring manual redesign, thus reducing development time while maintaining customization through template selection and parameter configuration.
Solution Approach 2:
The patent performs preliminary analysis of protocol specifications to automatically generate hardware architecture decisions, resource allocation, and optimization strategies before actual hardware design begins. This preliminary automated analysis prepares the hardware implementation plan in advance, reducing the time needed for manual design iterations.
2Productivity
If rapid hardware generation is implemented using automated methods, then development time is reduced, but the complexity of the generation system increases
Solution Approach 1:
The patent segments the hardware generation process into distinct modular components: protocol specification parsing, resource requirement analysis, hardware module selection, and configuration generation. Each segment is handled by specialized sub-systems that work independently but coordinate through standardized interfaces, making the overall complex system manageable and maintainable while achieving high generation speed.
3Manufacturing precision
If manual hardware design processes are used, then design quality and optimization can be ensured, but the development cost and time increase
Solution Approach 1:
The patent incorporates automated verification and validation mechanisms that provide feedback during the hardware generation process. The system analyzes generated hardware configurations against protocol requirements, performs resource allocation verification, and identifies potential optimization opportunities, ensuring design quality is maintained through automated quality checks rather than manual review.
Data Source
AI summary
A method is provided for scheduling a network packet processor. A textual language specification is input of the processing of network packets by the network packet processor. The textual language specification includes memory read actions and modification actions. Each memory read action reads a stored value from a memory of the network packet processor. Each modification action modifies a field of the network packets. An availability is determined for each field read from the network packets for the memory read and modification actions. An availability is determined for each stored value read from the memory for the memory read actions. A look-ahead interval is determined from the availabilities. A respective storage class is determined for the fields for the memory read and modification actions. The respective storage class is one of a bus, a register, and a register with bypass.