Packet Processor Hardware Acceleration for Routing Table Updates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Updating large routing and sFlow key tables in network devices requires numerous CPU transactions, limiting the rate at which these structures can be updated due to the need for thousands of read and write operations.
Innovation Solution
Implementing hardware-accelerated table update circuitry within the packet processor, such as a finite state machine, to perform operations like insertion and deletion of values in sorted lists without software interaction from the CPU, reducing the number of required accesses to a single access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software on the CPU performs read and write operations to update the routing table in the packet processor, then the routing table can be updated, but the update rate is limited due to the large number of required CPU transactions
Solution Approach 1:
The patent introduces a hardware accelerator as an intermediary component between the CPU and packet processor. This dedicated hardware circuit performs table update operations (insertions, deletions, modifications) autonomously using binary search algorithms, eliminating the need for CPU software to perform thousands of read/write transactions. The hardware accelerator acts as a mediator that handles the complex update logic, reducing CPU transactions to a single initiation command while maintaining data consistency across the routing table.
Solution Approach 2:
The patent replaces the software-based mechanical system (CPU executing update instructions) with a hardware-based system. The hardware accelerator implements binary search and table update operations in dedicated circuitry, substituting the sequential software execution model with parallel hardware operations. This substitution eliminates the overhead of software interpretation and enables simultaneous multiple operations, dramatically increasing update throughput.
2Speed
If faster interfaces between the CPU and packet processor are used, then read and write access speed improves, but the number of required read/write accesses remains high
Solution Approach 1:
The patent extracts the table update functionality from the CPU software and main interface path, placing it in a dedicated hardware accelerator. This extraction removes the burden of complex update operations from the CPU-packet processor interface, reducing it to simple command issuance. The hardware accelerator handles all the intricate binary search and data movement operations internally, eliminating the need for multiple fast interface transactions.
3Measurement precision
If the routing table is maintained as a sorted list for efficient searching, then lookup performance improves, but insertion and deletion operations require shifting multiple entries
Solution Approach 1:
The hardware accelerator performs preliminary actions by pre-calculating insertion points using binary search before actual data movement. The system determines the exact position where new entries should be inserted or where deletions should occur, then executes all necessary shifts in a coordinated hardware operation. This preliminary positioning enables efficient bulk operations that maintain sorted order without requiring sequential software processing of each shift operation.
Data Source
AI summary
A network device can include a main processor and a packet processor. A method is provided that includes storing a table of values in the packet processor, using the packet processor to receive from the main processor a value that can be used to update the table of values, and using acceleration hardware in the packet processor to update the table of values based on the value received from the main processor without any additional interaction with the software running on the main processor.