Packet Reassembly Using Content Addressable Memory Lookup
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Solution Overview
Problem
The existing packet processing technologies in information technology networks face significant latency due to the time-consuming process of segmentation and reassembly of network packets, which hampers efficient data communication.
Innovation Solution
A process that utilizes a content addressable memory to efficiently reassemble packet fragments by generating a reassembly key from the incoming fragment header, looking up a reassembly table, and determining a location offset in a reassembly buffer for storing incoming fragments, thereby reducing latency in packet forwarding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional segmentation and reassembly logic is used in network switches, then packets can be fragmented and reassembled, but significant latency is added to packet forwarding
Solution Approach 1:
The patent replaces traditional sequential processing logic with content addressable memory (CAM) based parallel lookup operations. The CAM structure enables simultaneous comparison of multiple packet fragment headers against reassembly rules, eliminating the time-consuming sequential processing that caused latency while maintaining accurate reassembly through deterministic lookup operations.
Solution Approach 2:
The patent pre-configures reassembly rules and fragment header patterns in the content addressable memory before packet processing begins. This preliminary setup allows the system to perform instant pattern matching and reassembly decisions without requiring complex runtime logic evaluation, thereby reducing forwarding latency while ensuring reliable reassembly.
2Manufacturing precision
If complex reassembly logic is implemented to handle various packet fragment scenarios, then reassembly accuracy improves, but processing time increases
Solution Approach 1:
The patent segments the reassembly logic into distinct, independently configurable rules stored in the content addressable memory. Each rule handles a specific fragment pattern or reassembly scenario, allowing parallel evaluation of multiple rules simultaneously. This segmentation maintains high reassembly precision by addressing each scenario explicitly while improving processing speed through parallel rule evaluation.
Solution Approach 2:
The patent changes the operational parameters of the reassembly system by transitioning from sequential logic execution to parallel CAM-based pattern matching. This parameter change enables the system to evaluate multiple reassembly rules simultaneously, maintaining precision through exact pattern matching while dramatically improving processing throughput.
3Measurement precision
If detailed packet header analysis is performed for each fragment, then reassembly accuracy is maintained, but processing complexity increases
Solution Approach 1:
The patent introduces content addressable memory as an intermediary between packet fragment input and reassembly decision output. The CAM structure pre-stores reassembly rules and fragment header patterns, serving as a mediator that performs detailed header analysis through parallel pattern matching without requiring complex processing logic in the main system. This maintains high fragment identification accuracy while simplifying the overall device complexity.
Data Source
AI summary
Reassembly of fragments into a packet comprises receiving an incoming fragment of a packet from a network wherein each fragment comprises a segment of the packet and a header, generating a reassembly key using selected information from the incoming fragment header wherein the selected information is the same for all fragments of the packet, checking a reassembly table in a content addressable memory to find an entry that includes a logic key matching the reassembly key, and using a content index in the found entry and a sequence number of the incoming fragment within the packet, to determine a location offset in a reassembly buffer area for storing the incoming fragment at said location offset in the reassembly buffer area for the packet for reassembly.