Packet Relaying Apparatus Adaptive Gate Control for 5G Low Delay
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Solution Overview
Problem
In 5G mobile communication systems, there is a demand for ultra-low delay in wired sections to support high-priority packets while ensuring efficient transmission of low-priority packets, but existing technologies like Time Aware Shaper (TAS) often result in output delays for low-priority packets due to prioritization methods that prevent their output even when high-priority packets are not being transmitted.
Innovation Solution
A packet processing apparatus with a processor that learns the cyclic pattern of packet flow rates to dynamically control the opening and closing of gates for high-priority and low-priority packets, allowing for efficient output of both types of packets by allocating time slots based on allowable delay thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If Time Aware Shaper (TAS) technology is used to prioritize high-priority packets, then output delay for high-priority packets is reduced, but output delay for low-priority packets increases because their output is prevented even when high-priority packets are not being transmitted
Solution Approach 1:
The patent applies dynamics by making the gate control adaptive rather than static. The control unit dynamically adjusts gate opening/closing based on real-time packet arrival information and pre-stored cyclic patterns, allowing the system to transition between priority-based blocking and normal transmission based on actual traffic conditions, thus resolving the contradiction between low delay for high-priority and throughput for low-priority packets
Solution Approach 2:
The patent implements feedback mechanisms where the control unit monitors packet arrival information and compares it with pre-stored cyclic patterns to determine optimal gate control. This feedback loop allows the system to learn from actual traffic patterns and adjust gate states accordingly, preventing unnecessary blocking of low-priority packets while maintaining priority for high-priority packets when needed
2Loss of time
If the gate for low-priority packets is closed to ensure high-priority packet transmission, then high-priority packet delay is reduced, but low-priority packet transmission efficiency deteriorates
Solution Approach 1:
The system dynamically adjusts gate control based on actual traffic conditions rather than using fixed blocking. The control unit monitors packet arrivals and compares them with cyclic patterns to determine when to open/close gates, allowing low-priority packets to be transmitted when high-priority traffic is absent, thus maintaining transmission quantity while ensuring priority when needed
Solution Approach 2:
The control unit pre-stores cyclic patterns of packet flow rates and uses this preliminary information to predict optimal gate control timing. By comparing real-time packet arrival information with these pre-stored patterns, the system can proactively adjust gate states to prevent delays without unnecessarily blocking low-priority packet transmission
Data Source
AI summary
A packet processing apparatus sets, for each TS as a gate state of each of a first gate and a second gate, a priority state, a normal state, and a mixed state and sets a predetermined TS associated with a cyclic pattern of the first packet to the priority or the mixed state. The apparatus allocates, when an amount of output delay of the first packet that is in the mixed state in the predetermined TS is within an allowable amount, the first packet and the second packet to the predetermined TS. The apparatus sets output timing of the first packet allocated in the predetermined TS to the priority state and sets output timing of the second packet allocated in the predetermined TS to the normal state.