Packet Reorder Block for In-Order Delivery
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Solution Overview
Problem
In packet processing systems, the variable processing times for different packet manipulations, such as adding headers or encrypting packets, can cause packets to leave the processing unit in a different order than they entered, leading to unordered packet delivery.
Innovation Solution
The Network Flow Processor (NFP) includes a packet reorder block, a memory unit with buffers, and a scheduler block, which uses sequence numbers and valid bits to ensure in-order packet delivery by determining when packets are ready to be output and storing or transmitting them accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If packets are processed with variable processing times for different manipulations, then packet processing flexibility is improved, but packet delivery order is worsened
Solution Approach 1:
The system segments packet processing into multiple independent manipulation stages (header addition, tagging, classification, encryption), each handled by separate processing units. This allows variable processing times for different packet types while maintaining overall order through the segmented architecture where packets progress through stages in sequence.
Solution Approach 2:
A reorder buffer acts as an intermediary between the processing units and the output interface. The buffer receives packets from various processing stages with different completion times and rearranges them to maintain original order, mediating between processing flexibility and delivery reliability.
2Productivity
If multiple packets are processed concurrently with different manipulation times, then processing throughput is improved, but packet ordering is worsened
Solution Approach 1:
The system attaches sequence numbers to packets before processing begins. This preliminary action allows the reorder buffer to later sort and rearrange packets based on their original sequence, enabling concurrent processing while preserving order information for correct delivery.
Solution Approach 2:
The reorder buffer serves as an intermediary that decouples concurrent processing from ordered delivery. It temporarily stores packets arriving from different processing stages and outputs them in the correct sequence, allowing high throughput while maintaining reliability.
3Reliability
If packets are stored in buffers for reordering, then packet delivery order is improved, but memory requirements are worsened
Solution Approach 1:
The reorder buffer is implemented with differentiated buffer sizes for different packet types and priorities. Critical packets receive larger buffer allocation while less critical packets use smaller buffers, optimizing memory usage while maintaining reordering capability for all packet types.
Solution Approach 2:
The buffer allocation is dynamic rather than static. The system adjusts buffer assignments based on real-time packet characteristics, flow types, and memory availability, allowing efficient memory utilization while ensuring correct packet ordering for all active flows.
Data Source
AI summary
Circuitry to provide in-order packet delivery. A packet descriptor including a sequence number is received. It is determined in which of three ranges the sequence number resides. Depending, at least in part, on the range in which the sequence number resides it is determined if the packet descriptor is to be communicated to a scheduler which causes an associated packet to be transmitted. If the sequence number resides in a first “flush” range, all associated packet descriptors are output. If the sequence number resides in a second “send” range, only the received packet descriptor is output. If the sequence number resides in a third “store and reorder” range and the sequence number is the next in-order sequence number the packet descriptor is output; if the sequence number is not the next in-order sequence number the packet descriptor is stored in a buffer and a corresponding valid bit is set.


