Packet Reordering Engine Using Buffer Descriptors to Cut On-Chip RAM
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Solution Overview
Problem
Existing data communications networks face challenges in correcting out-of-order delivery of data packets due to varying paths and processing procedures, requiring large on-chip RAM to store all packets, which is inefficient.
Innovation Solution
A two-step method using a packet buffer address in on-chip RAM based on sequence numbers, allowing smaller RAM usage by storing packet payloads in DRAM and fetching them in order, with a packet reordering engine that reorders using a reorder buffer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the payload of each received packet is written to an on-chip RAM at a location corresponding to the sequence number, then packets can be read out in the intended order, but the on-chip RAM must be large enough to store all packet payloads being processed
Solution Approach 1:
The patent divides the storage system into two segments: on-chip RAM stores only buffer descriptors (metadata) while off-chip DRAM stores the actual packet payloads. This segmentation allows the on-chip RAM to remain small while still enabling packet reordering functionality.
Solution Approach 2:
The patent extracts the packet payload storage function from the on-chip RAM and relocates it to off-chip DRAM. The on-chip RAM retains only the essential buffer descriptor information needed for reordering, dramatically reducing its required capacity.
2Reliability
If a large on-chip RAM is used to store all packet payloads for reordering, then correct packet ordering is achieved, but the device complexity and resource consumption increase
Solution Approach 1:
The memory architecture is segmented into on-chip RAM for metadata and off-chip DRAM for payloads, simplifying the on-chip resource requirements while maintaining reordering capability.
Solution Approach 2:
Buffer descriptors act as intermediaries between the packet reception system and the ordering system. These descriptors contain sequence number information that enables reordering without requiring the full packet data to be present in fast memory.
Data Source
AI summary
An apparatus is described and includes a packet reordering engine (PRE) for reordering data packets stored in a packet buffer at locations identified by buffer descriptors (BD). The PRE includes a BD fetch manager for fetching BDs associated with the stored data packets; a header decoder module for fetching the header portion for the stored data packets associated with the fetched BDs; a reorder module for receiving the fetched BDs and the fetched header portions and storing the fetched BD associated with the data packet in a slot of the reorder buffer; and a buffer processor configured to receive BDs from the reorder module in an order indicated by the header information of the data packets associate with the BDs and to fetch the payloads of the data packets with which the received BDs are associated from the packet buffer.