Packet Resequencing Across Multi-Core Network Processing
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Solution Overview
Problem
Packet misordering occurs when using multiple cores for processing, leading to congestion controller confusion, network performance degradation, and increased latency due to misinterpretation of packet order by congestion control algorithms.
Innovation Solution
A hardware-based sequencing and resequencing system that assigns sequence numbers to packets before distribution across multiple cores, ensuring packets are reordered correctly upon output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple cores are used to process packets in parallel, then processing speed and productivity are improved, but packet ordering is lost causing misordering
Solution Approach 1:
The patent applies preliminary action by assigning sequence numbers to packets before they are distributed to multiple cores. The hardware sequencer tags each packet with its original sequence number prior to parallel processing, enabling later reordering without requiring complex coordination during processing.
Solution Approach 2:
The patent uses sequence number metadata as an intermediary to track packet origins. This metadata acts as a mediator between the parallel processing cores and the output queue, allowing the hardware resequencer to correctly reorder packets based on their original sequence numbers without software intervention.
2Productivity
If packets are offloaded to multiple cores for processing, then system performance is improved, but congestion control algorithms become confused due to misordering
Solution Approach 1:
The hardware sequencer performs preliminary action by capturing the original packet sequence numbers before parallel processing begins. This preserved ordering information ensures that congestion control algorithms receive packets in the correct order at the output, preventing algorithm confusion while maintaining the performance benefits of multi-core processing.
3Stability of the object's composition
If packet reordering is performed by software, then packet order can be maintained, but processing time increases due to software bottlenecks
Solution Approach 1:
The patent replaces software-based reordering mechanisms with a hardware solution. The hardware sequencer and resequencer use dedicated hardware circuits to assign and process sequence numbers, eliminating the need for software to perform time-consuming reordering operations while maintaining packet order integrity.
Solution Approach 2:
By performing sequence number assignment and packet tagging in hardware before packets enter the parallel processing pipeline, the system eliminates the need for subsequent software-based reordering operations, reducing processing time while maintaining order.
4Stability of the object's composition
If single core is used to process packets, then packet order is maintained, but processing throughput is limited
Solution Approach 1:
The patent segments the packet processing function across multiple hardware cores while using sequence number metadata to maintain logical ordering. This segmentation enables parallel processing throughput while the resequencing mechanism ensures ordered delivery, resolving the trade-off between single-core order preservation and multi-core throughput.
Data Source
AI summary
An accelerator device and system are described, among other things. An illustrative system is disclosed to include a first sequencer programmed to append packets with information identifying a sequence number and an identification of a flow with which each packet is associated. The appended information may be used by a second sequencer to resequence the packets.