Packet Reshuffler Circular Shift Register Logic High-Speed Flow Control
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Solution Overview
Problem
Implementing transmitter-controlled flow control in high-speed RAPIDIO systems is challenging due to the difficulty in sequentially inspecting packets to determine the next packet for transmission, leading to buffer gaps and potential stalls.
Innovation Solution
A packet reshuffler using circular shift register logic, encoder logic, and selection logic to manage pointers for packets, allowing for efficient reordering and prioritization without sequential inspection, utilizing a combinatorial logic to control the reshuffling process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential inspection of packets is used to determine the next packet for transmission, then the transmitter can implement flow control according to packet priorities, but the transmission speed decreases and buffer gaps are created
Solution Approach 1:
The patent pre-calculates and stores the next packet to be transmitted in advance using a state machine and buffer management system. Instead of sequentially inspecting packets during transmission, the system prepares the next packet's selection criteria and candidate packets beforehand, allowing immediate transmission without inspection delays.
Solution Approach 2:
The patent introduces an intermediary buffer management system that sits between the packet queue and the transmission interface. This intermediary pre-processes packet selections and maintains a ready-state packet buffer, acting as a mediator that eliminates the need for real-time sequential inspection during the critical transmission path.
2Reliability
If sequential packet inspection is performed to select the next packet, then priority-based flow control is achieved, but buffer gaps are created and stalls may occur
Solution Approach 1:
The system performs preliminary packet selection and validation before the transmission slot becomes active. The state machine pre-determines which packet should be transmitted next based on priority criteria, and the buffer is pre-loaded with the selected packet, eliminating time loss during actual transmission.
Solution Approach 2:
The patent ensures continuous useful action by maintaining a always-ready packet in the transmission buffer. The pre-selection mechanism ensures that there is never a gap or stall because the next packet is already identified and positioned for immediate transmission, keeping the transmission pipeline continuously active.
3Productivity
If high-speed transmission is implemented, then productivity increases, but sequential inspection becomes too slow to prevent stalls
Solution Approach 1:
The system performs all packet selection operations preliminarily, before the high-speed transmission phase. The state machine and buffer management complete the selection process in advance, so during high-speed transmission, packets are simply transferred without requiring slow sequential inspection operations.
Solution Approach 2:
The patent replaces the mechanical sequential inspection process with a state-machine-based control system that uses pre-computed selection logic. This substitution eliminates the need for step-by-step packet examination during transmission, enabling high-speed operation while maintaining proper packet selection based on priorities.
Data Source
AI summary
A packet reshuffler and a method of implementing the same is described. In one example, a digital logic circuit in a transmitter for sending packets stored in a set of buffers includes circular shift register logic, encoder logic, selection logic, and combinatorial logic. The circular shift register logic includes a plurality of registers configured to respectively store a plurality of pointers. Each of the plurality of pointers includes an address of one of the buffers, a priority value, and a type value. The encoder logic is configured to produce a plurality of sets of bits respectively associated with the plurality of pointers. The selection logic is configured to process the plurality of sets of bits to generate a shuffle entry signal associated with a selected one of said plurality of pointers. The combinatorial logic is configured to control the circular shift register logic in response to the shuffle entry signal.