Cross-Protocol Packet Routing With Lane and Clock Translation
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Solution Overview
Problem
Computing systems face challenges in interfacing with busses of different protocols and bus sizes due to incompatibilities in timing, protocols, and bus widths, leading to complex solutions with high gate counts.
Innovation Solution
A system and method for translating packets between two data bus systems using a dual-port RAM system with a state machine synchronized to different clocks, utilizing egress and ingress selectors and memories to manage data transfer between PCIe and AXI bus interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a dual-port random access memory (RAM) for each direction is used in conjunction with sets of registers/flops and barrel shifters, then packet translation between different bus protocols is achieved, but device complexity and gate count increase significantly
Solution Approach 1:
The patent divides the packet translation function into separate ingress and egress path components, each with dedicated selectors and memories. This segmentation allows independent optimization of each direction's translation logic, reducing the need for complex dual-port memory structures and associated control logic, thereby lowering overall gate count while maintaining translation capability.
Solution Approach 2:
The patent employs universal selector structures that can handle multiple bus protocols and packet formats through configurable selection logic. These selectors serve multiple functions by dynamically routing different packet types between ingress and egress paths, eliminating the need for dedicated hardware for each protocol translation scenario and reducing overall device complexity.
2Adaptability or versatility
If bus interfaces with different numbers of lanes are used, then compatibility with various bus standards is improved, but the complexity of data routing and synchronization increases
Solution Approach 1:
The patent implements dynamic lane selection where the number of active ingress and egress lanes can be configured based on the specific bus standard being used. This dynamic adaptability allows the same hardware structure to accommodate different lane configurations (e.g., 10 lanes for PCIe, 16 lanes for AXI) without requiring dedicated routing logic for each standard, thereby reducing routing complexity while maintaining compatibility.
Data Source
AI summary
An apparatus and method coupling a first and a second data bus comprising selectors for routing first bus egress lanes to egress memories, each egress memory coupled to one second bus egress lane, where the second bus has more egress lanes than the first. Each egress memory corresponds to one second bus egress lane. A first FSM selecting which first bus egress lane to load into each egress memory synchronous with the first bus clock. A second FSM outputting egress memory values to the second bus synchronous with the second bus clock. A set of ingress memories, each memory coupled to one second bus ingress lane and to an input of each ingress selector. A third FSM loading the ingress memories synchronous with the second bus clock. A fourth FSM selecting which ingress memory to route to each first bus ingress lane synchronous with the first bus clock.