Packet-Based Routing for Multi-Chip Sub-Nanosecond Latency
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Solution Overview
Problem
Conventional multi-chip systems face challenges in routing low-latency memory traffic due to fixed interconnect topologies and complex self-identification protocols, which become inadequate for future 3D-stack systems requiring sub-nanosecond communication mechanisms.
Innovation Solution
A packet-based routing system where each semiconductor chip generates a packet with a header containing identification information for efficient routing across substrates and nodes, allowing for flexible routing algorithms and bandwidth management without requiring prior global information about other chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed interconnect topologies and complex self-identification protocols are used in conventional multi-chip systems, then routing flexibility and adaptability are improved, but communication latency increases and sub-nanosecond communication mechanisms cannot be achieved
Solution Approach 1:
The routing system is segmented into independent routing decisions at each node, where packets are forwarded based on local routing table lookups rather than global fixed topology constraints. Each node independently determines the next hop based on destination address, enabling flexible routing paths without system-wide coordination overhead.
Solution Approach 2:
The routing system transitions from static fixed topology to dynamic adaptive routing using routing tables that can be programmed and updated. Routing decisions are made dynamically at each node based on current routing information, allowing the system to adapt to different communication patterns and optimize latency for specific traffic types.
2Loss of time
If uniform packet-based routing system is implemented across all chips, then communication latency is reduced and routing efficiency is improved, but device complexity increases due to packet header processing requirements
Solution Approach 1:
The packet header containing routing information is extracted and processed separately from the payload data. Routing decisions are made based on the header information at each node, allowing the data payload to be transmitted efficiently without repeated processing overhead. The header is handled by routing logic while the payload passes through the interconnect.
Solution Approach 2:
Routing information is prepared in advance and embedded in the packet header before transmission begins. Routing tables are pre-programmed with destination-to-next-hop mappings, allowing nodes to make rapid forwarding decisions without complex real-time calculations. This preliminary preparation of routing information reduces per-packet processing complexity.
3Ease of manufacture
If disparate chip architectures with different on-chip networks are used, then chip design independence and manufacturing flexibility are maintained, but system-wide routing efficiency deteriorates and uniform low-latency communication cannot be achieved
Solution Approach 1:
A universal packet format and routing protocol is implemented that can carry traffic between different chip architectures through the shared interposer network. The packet-based interface provides a common language for heterogeneous chips, allowing each chip to maintain its internal architecture independence while achieving efficient system-wide communication through the standardized interconnect protocol.
Data Source
AI summary
Various methods, computer-readable mediums, articles of manufacture and systems are disclosed. In one aspect, a method is provided that includes generating a packet with a first semiconductor chip. The packet is destined to transit a first substrate and be received by a node of a second semiconductor chip. The packet includes a packet header and packet body. The packet header includes an identification of a first exit point from the first substrate and an identification of the node. The packet is sent to the first substrate and eventually to the node of the second semiconductor chip.