Packet Scheduler Throughput via Deficit Extraction
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Solution Overview
Problem
Current packet scheduling algorithms, such as Deficit Round Robin (DRR), are inefficient on slower hardware platforms like FPGAs, requiring many cycles and arithmetic operations, and cannot keep up with faster data links like 200 Gigabit Ethernet, due to their critical feedback path and inability to be pipelined.
Innovation Solution
A packet scheduler implementing fair queueing with a basic round robin scheduler that achieves single-cycle-per-packet throughput by removing deficit calculation from the critical loop, allowing for higher packet rates and larger queue counts, and using a traffic manager to throttle over-allocated queues, ensuring fair queuing in a latency-insensitive manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Deficit Round Robin (DRR) algorithm is implemented on FPGA, then fair queueing can be achieved, but the scheduling decision takes many computing cycles and cannot keep up with fast data links
Solution Approach 1:
The patent extracts the deficit calculation operation from the critical scheduling loop. The round robin scheduler selects packets without performing deficit calculations, and the deficit update is performed separately in a non-critical path, allowing the scheduling decision to be made in a single cycle while still achieving fair queueing
Solution Approach 2:
The patent performs preliminary actions by pre-calculating or preparing queue status information before the scheduling cycle begins. The traffic manager prepares deficit values and queue priority information in advance, so that the scheduler can make decisions based on pre-processed data without performing complex calculations during the critical scheduling path
2Reliability
If DRR algorithm is implemented on slower hardware platforms, then fair queueing can be achieved, but many arithmetic operations are required making it inefficient
Solution Approach 1:
The patent removes the arithmetic-intensive deficit calculation from the critical scheduling path. The scheduler only performs simple comparisons and selections, while deficit updates are performed separately using simpler arithmetic operations that do not impact the scheduling decision timing
Solution Approach 2:
The patent uses simplified, approximate deficit calculations that are computationally cheaper than exact DRR calculations. The traffic manager uses coarse-grained deficit tracking that provides sufficient fairness guarantees without requiring precise arithmetic operations, reducing the computational burden on hardware platforms
3Ease of manufacture
If basic round robin scheduling is used, then simple implementation is achieved, but bandwidth allocation is unfair among different data streams
Solution Approach 1:
The patent introduces a traffic manager as an intermediary between the simple round robin scheduler and the queues. The traffic manager monitors bandwidth usage, calculates deficit values, and adjusts queue priorities or throttles queues to enforce fair bandwidth allocation, while the scheduler itself remains a simple round robin implementation
Solution Approach 2:
The patent implements feedback mechanisms where the traffic manager continuously monitors the bandwidth allocated to each queue and adjusts scheduling parameters accordingly. Deficit values are updated based on actual bandwidth consumption, and this feedback is used to throttle or enable queues to achieve fair bandwidth distribution over time
Data Source
AI summary
An integrated circuit includes queue circuits for storing packets, a scheduler circuit that schedules the packets received from the queue circuits to be provided in an output, and a traffic manager circuit that disables one of the queue circuits from transmitting any of the packets to the scheduler circuit based at least in part on a bandwidth in the output scheduled for a subset of the packets received from the one of the queue circuits.