Packet Scheduling Using Deficit Round Robin for Fair Bandwidth Allocation

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Solution Overview

Problem

Existing packet scheduling algorithms face challenges in achieving fair bandwidth allocation, reducing congestion, and minimizing packet losses, particularly during busy periods, with many techniques resulting in large queuing delays and complex hardware implementations.

Innovation Solution

A packet scheduling method that updates credit or deficit values for each queue in a round-robin fashion, prioritizing packets with no deficit for transmission and allocating credits based on proportional weights to ensure fair bandwidth distribution and reduce congestion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If timestamp schedulers are used to emulate GPS operation, then fairness in bandwidth allocation is improved, but device complexity increases due to sorting bottleneck and complicated data structures

Engineering Contradiction:
Improvebandwidth allocation fairnessVSAvoiddata structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses simple circular buffer structures with fixed-size entries that are continuously overwritten, replacing complex dynamic data structures. Each buffer entry is a simple structure with packet pointer, length, and timestamp fields, designed for efficient hardware implementation without complex memory management.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent replaces the software-based sorting mechanism of timestamp schedulers with a hardware-friendly circular buffer approach that uses simple comparison logic. Instead of implementing full sorting algorithms, the system uses deficit counter comparisons and round-robin selection that can be directly implemented in hardware logic.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Device complexity

If round-robin schedulers are used to achieve O(1) time complexity, then device complexity is reduced, but delay properties worsen due to transmitting all data of a flow at once

Engineering Contradiction:
Improvescheduling algorithm complexityVSAvoidpacket delay
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent segments the transmission of each flow's data across multiple rounds rather than transmitting all data in a single round. The deficit counter mechanism allows a flow to transmit only the portion of its data that fits within its allocated quantum, with the remainder deferred to subsequent rounds, thereby spreading transmission over time and reducing burstiness.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic credit allocation based on flow weights and actual transmission needs. The deficit counter is dynamically adjusted each round based on the flow's weight and the amount of data actually transmitted, allowing the scheduler to adapt to varying traffic conditions while maintaining O(1) complexity through simple counter updates.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If Deficit Round Robin is used to achieve O(1) time complexity, then device complexity is reduced, but delay and burstiness properties worsen especially for flows with large weights

Engineering Contradiction:
Improvescheduling algorithm complexityVSAvoidpacket delay and burstiness
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent modifies the deficit round robin parameters by introducing weight-based credit allocation and a minimum transmission threshold. Flows with large weights receive proportionally larger credits, but the actual transmission is constrained by the minimum threshold and the flow's available data, preventing excessive burstiness while maintaining fairness for high-weight flows.

Inventive Principle:
Principle #35Parameter changes

4Loss of time

If Smoothed Round Robin is used to improve delay properties, then packet delay is reduced, but device complexity increases due to Weight Spread Sequence and Weight Matrix data structures

Engineering Contradiction:
Improvepacket delayVSAvoiddata structure complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent replaces the complex Weight Spread Sequence and Weight Matrix data structures with simple circular buffers and deficit counters. The scheduling decision is based on straightforward comparisons of deficit counters and weight-based credit allocations, eliminating the need for complex pre-computed sequences and matrices while achieving similar delay performance.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS7646717B1Method and apparatus for packet scheduling
Publication Date: 2010.01.12 MARVELL ASIA PTE LTD
  • US7646717B1 patent drawing
  • US7646717B1 patent drawing
  • US7646717B1 patent drawing

AI summary

A methods, apparatus and computer memory are provided for packet scheduling. A processor polls queues in a round robin fashion and schedules for transmission onto a link a packet in each queue with no deficit before scheduling for transmission onto the link a packet in each queue with a deficit. A credit is allocated to each queue with the deficit based on a proportional weight, until each queue with the deficit has a credit.