Packet Search Acceleration via Primary-Secondary Array Filtering
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Solution Overview
Problem
Existing communication networks face inefficiencies in matching incoming packets with memory locations due to large buffer entry sizes and high latency costs associated with serial search methods in linked lists, making it impractical to store and access all buffer entries in memory on a network interface card (NIC).
Innovation Solution
Implementing search acceleration logic on the NIC to match incoming packets using a primary array with tags and digests, where the primary array stores a subset of matching criteria, allowing for parallel processing and reducing latency by filtering out non-matching entries, and using a secondary array for full entries, enabling faster search times and higher hit rates compared to direct-mapped caches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If serial search methods in linked lists are used to match incoming packets with memory locations, then the system can handle large buffer entry sizes, but the latency increases significantly
Solution Approach 1:
The patent segments the buffer entry matching process into two distinct phases: (1) a fast filter phase that compares only critical fields (packet length, source/destination addresses) to quickly eliminate non-matching entries, and (2) a slower full comparison phase that only processes entries passing the filter. This segmentation reduces average search time while maintaining the ability to handle large buffer entries.
Solution Approach 2:
The patent applies partial action by performing only a subset of the full buffer entry comparison initially. Instead of comparing all fields of every buffer entry with every incoming packet, the system performs a partial comparison on key fields first, and only proceeds to full comparison when necessary. This dramatically reduces the average number of comparisons required.
2Reliability
If all buffer entries are stored in memory on the NIC, then complete packet matching capability is achieved, but the device complexity and memory requirements become impractical
Solution Approach 1:
The patent extracts only the essential matching fields from full buffer entries and stores them in a compact filter structure on the NIC. The extracted fields include packet length, source address, and destination address - the minimum information needed to perform initial filtering. Full buffer entries are kept in host memory, and only matching entries are retrieved when needed.
Solution Approach 2:
The patent introduces an intermediary data structure (the filter entry) that sits between the full buffer entries in host memory and the incoming packet matching process. This filter entry contains only the critical fields needed for quick comparison, acting as a mediator that enables fast preliminary filtering without requiring full buffer entries to be present on the NIC.
3Speed
If direct-mapped caches are used for packet matching, then access speed is improved, but the hit rate decreases compared to other cache structures
Solution Approach 1:
The patent implements a dynamic caching strategy where the system adapts to workload patterns by allowing multiple buffer entries to share cache lines when they have identical filter keys. The cache structure dynamically adjusts its behavior based on the specific matching requirements, switching between direct-mapped and set-associative access patterns depending on the distribution of packet attributes in the current workload.
Data Source
AI summary
Logic may store at least a portion of an incoming packet at a memory location in a host device in response to a communication from the host device. Logic may compare the incoming packet to a digest in an entry of a primary array. When the incoming packet matches the digest, logic may retrieve a full entry from the secondary array and compare the full entry with the first incoming packet. When the full entry matches the first incoming packet, logic may store at least a portion of the first incoming packet at the memory location. And, in the absence of a match between the first incoming packet and the digest or full entry, logic may compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.