Packet Selection for IEEE 1588 Clock Synchronization
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Solution Overview
Problem
Packet delay variation (PDV) significantly affects the accuracy and stability of slave clocks in IEEE 1588 Precision Time Protocol (PTP) networks, leading to clock noise and poor synchronization performance, especially in end-to-end timing transfer scenarios where intermediate network devices introduce variable delays.
Innovation Solution
A packet selection technique that determines an optimal inter-arrival time for packets and selects those with inter-arrival times closest to this optimal time, reducing PDV and improving clock synchronization by using packets with minimal delay variation for clock recovery mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If packet selection is performed to reduce PDV, then clock synchronization accuracy is improved, but device complexity increases
Solution Approach 1:
The patent changes the selection criterion from complex multi-parameter analysis to a simple inter-arrival time parameter comparison. By determining an optimal inter-arrival time and selecting packets whose inter-arrival times closest match this optimal value, the system achieves PDV mitigation through a single, easily calculable parameter rather than complex algorithms analyzing multiple packet characteristics.
Solution Approach 2:
The packet selection mechanism uses information already present in the packet timing data itself (inter-arrival times) to perform the selection, rather than requiring external complex processing. The optimal inter-arrival time is determined from the packet stream itself, and the same packet stream provides the data needed for selection, making the system self-sufficient and reducing external processing complexity.
2Productivity
If all received packets are used for clock recovery, then productivity is improved, but clock noise increases due to PDV
Solution Approach 1:
The patent extracts only the packets with inter-arrival times closest to the optimal value from the complete packet stream for clock recovery processing. By taking out and selecting only these specific packets rather than using all packets, the system removes the harmful PDV-induced noise while maintaining efficient clock recovery using a subset of the most suitable packets.
3Object-affected harmful factors
If packet selection based on inter-arrival time is implemented, then PDV mitigation is improved, but measurement precision requirements increase
Solution Approach 1:
The patent applies partial action by selecting only those packets whose inter-arrival times are closest to the optimal value, rather than requiring perfect precision for all packets. This partial selection approach mitigates PDV impact effectively while reducing the stringent precision requirements that would be needed if all packets were processed with perfect accuracy.
Data Source
AI summary
This invention relates to packet selection techniques that can be used in conjunction with a clock recovery mechanism to mitigate the effects of packet delay variation on timing messages exchanged over a packet network, particularly when seeking to synchronize the time of a clock in a slave device to that of a master clock. The packet selection techniques can assist in reducing the noise in the recovered clock signal at the slave device, allowing recovery to a higher quality. Embodiments of the invention provide techniques based on extracting timing packets that create a constant interval between the arrival of selected packets at the slave device and on extracting timing packets which are closest to making the interval between arrival of the selected packets equal to the interval between the departure of the packets.