Packet Sorting and Reassembly Circuit for Out-of-Sequence TCP Segments
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Solution Overview
Problem
During high-speed packet transmission, out-of-sequence packet segments can lead to incorrect reassembly, hindering the efficient retrieval of packet content, particularly in systems requiring security protection and risk-control, where timely analysis is crucial.
Innovation Solution
A packet sorting and reassembly circuit module comprising a header parser, information processing circuit, state tracking and reassembly circuits, and an output arbiter, implemented in hardware, which analyzes packet segments, extracts sideband information, and reassembles them efficiently using the AXI4-Stream protocol to maintain high-speed transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If packet segments are transmitted at high speed, then transmission efficiency is improved, but packet segments may arrive out of sequence making reassembly difficult
Solution Approach 1:
The patent applies preliminary action by extracting and processing packet header information (including sequence numbers) before the main packet data arrives. The header parser prepares sorting information in advance, allowing the reassembly circuit to immediately correctly sequence packet segments upon their arrival, even when transmitted at high speeds out of order.
Solution Approach 2:
The patent introduces an intermediary mechanism - the header information and sequence number extraction system - that mediates between the high-speed incoming packet segments and the reassembly process. This intermediary parses header data first, creates sorting references, and enables the reassembly circuit to correctly order segments without slowing down the overall transmission speed.
2Productivity
If packet segments are sorted and reassembled in hardware circuit, then reassembly efficiency is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the packet processing function into distinct hardware modules: a header parser for extracting sequence information, an information processing circuit for intermediate processing, and a reassembly circuit for final ordering. This modular segmentation achieves high reassembly efficiency through parallel hardware operation while managing complexity through functional decomposition.
Solution Approach 2:
The patent replaces software-based packet reassembly with a dedicated hardware circuit implementation. By substituting the mechanical/software processing system with an electronic hardware circuit that operates at wire-speed, the system achieves significantly higher reassembly efficiency while the modular circuit design keeps complexity manageable.
3Device complexity
If all packet segments are processed through the same reassembly circuit, then processing is simplified, but transmission speed decreases due to sequential processing
Solution Approach 1:
The patent applies preliminary action by having the header parser extract and prepare sequence information for multiple packet segments simultaneously before they reach the reassembly stage. This advance preparation enables the reassembly circuit to process multiple segments in parallel rather than sequentially, increasing speed while keeping the reassembly logic itself relatively simple.
Data Source
AI summary
A packet sorting and reassembly circuit module, including a header parser, an information processing circuit, at least one state tracking and reassembly circuit, and an output arbiter, is provided. The header parser is configured to analyze multiple first packet segments to obtain header information corresponding to a first network packet, wherein the first network packet is transmitted based on a transmission control protocol (TCP) communication protocol. The information processing circuit is configured to transmit the first packet segments and sideband information corresponding to the first packet segments to a first state tracking and reassembly circuit among the at least one state tracking and reassembly circuit according to the header information. The first state tracking and reassembly circuit is configured to reassemble and sort the first packet segments according to the sideband information. The output arbiter is configured to output the first packet segments according to a sorting result.