Network Packet Storage Using Burst Mode DRAM Access
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Solution Overview
Problem
Existing network packet switching technologies face inefficiencies due to high overhead access times in Dynamic Random Access Memory (DRAM) when handling large volumes of packet data, particularly at high speeds, leading to increased memory requirements and economic impracticalities with multiple DRAM controllers or wasted bandwidth with single DRAM setups.
Innovation Solution
A network packet transmitting apparatus and method that uses a single DRAM controller, employing burst mode data transmission and efficient storage management by aggregating packet data and control information into blocks, dynamically adjusting memory usage, and prioritizing storage rows to minimize overhead accesses and optimize access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single DRAM controller is used, then device complexity is reduced, but overhead access time increases due to sequential row activation requirements
Solution Approach 1:
The patent segments the DRAM access process into two independent phases: row activation phase (for control information) and data reading/writing phase. By separating these phases and using burst mode for data transfers, the system reduces overhead access time while maintaining a single DRAM controller, thus resolving the contradiction between device complexity and time loss.
Solution Approach 2:
The patent implements preliminary row activation before data transfers. The control information is first written to activate the necessary DRAM rows, and then data blocks are transferred in burst mode. This preliminary action ensures that when data needs to be read or written, the rows are already active, eliminating additional overhead access time during data operations.
2Productivity
If multiple DRAM controllers are used, then access efficiency improves, but device complexity and cost increase
Solution Approach 1:
The patent uses burst mode to enable continuous data transfer without interruption. Once a row is activated, multiple data blocks can be read or written in a continuous burst sequence without returning to the inactive state. This continuity of useful action maintains high access efficiency with a single DRAM controller, eliminating the need for multiple controllers while preserving productivity.
3Adaptability or versatility
If row address is changed each time DRAM is accessed, then data can be retrieved from different locations, but overhead access time increases due to active bank/row and pre-charge requirements
Solution Approach 1:
The patent performs row activation as a preliminary action before data retrieval. Control information is first written to the DRAM to activate the necessary rows, establishing the memory state in advance. Subsequent data blocks are then accessed without repeating the row activation sequence, as the rows remain active during burst mode transfers. This resolves the contradiction by preparing the memory system beforehand.
Solution Approach 2:
The patent maintains continuous data transfer operations in burst mode once rows are activated. Multiple data blocks can be accessed sequentially without changing row addresses or performing additional activation cycles. This continuous operation maintains adaptability for retrieving data from different locations while eliminating repeated overhead accesses, thus resolving the time loss issue.
4Adaptability or versatility
If packet data is stored in discrete segments on DRAM, then data can be stored from different sources, but additional information is required to record exact addresses for reconstruction
Solution Approach 1:
The patent merges control information and data blocks into a unified storage structure. Control information includes the starting address and length of data blocks, allowing the system to reconstruct continuous data sequences from stored segments without requiring additional address metadata. This merging approach maintains storage flexibility while reducing information loss, as the control data itself contains the necessary addressing information for reconstruction.
Data Source
AI summary
A network packet storage method and network packet transmitting apparatus using the same is provided. A packet content and a path control information are obtained from a received packet, and a packet storage address of the packet content is determined according to a predetermined storage rule. The packet content is stored in a data block and packet storage addresses and path control information of packets output via the same output port are stored in a control block. The data block is output when its size reaches a predetermined data block size such that a dynamic random access memory receives the data block by using burst mode. Further, the control block is output when its size reaches a predetermined control block size.