Packet-Based Streaming Network for SOC Test I/O Reduction
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Solution Overview
Problem
The complexity of hierarchical scan test in Systems-On-A-Chip (SOCs) increases with the number of core hierarchy levels, leading to sub-optimal results due to limited chip-level I/Os, routing congestion, and dependencies between core and top-level designs, making it difficult to access and test multiple cores simultaneously.
Innovation Solution
A system for streaming data to circuit blocks using a first network with configurable data channels and interface devices that transport data packets with m bits, where m is greater than or equal to the number of data channels, and a second network for configuration data, allowing efficient testing of multiple cores with reduced chip-level I/O requirements through packet-based access architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional point-to-point scan access methods are used to connect chip-level I/Os to core-level channels, then direct access to cores is achieved, but the number of cores that can be tested concurrently is limited due to limited chip-level I/Os
Solution Approach 1:
The patent introduces a packet-based access architecture with interface devices acting as intermediaries between chip-level I/Os and core-level channels. These interface devices receive packets containing multiple bits, each bit assigned to different circuit blocks, enabling one I/O to access multiple cores simultaneously through a single packet interface, thus removing the direct one-to-one connection constraint
Solution Approach 2:
The patent transitions from a one-dimensional point-to-point connection model to a multi-dimensional packet-based model where a single I/O can address multiple cores through packet routing. The packet structure allows bits to be assigned to different circuit blocks, creating a new dimension of access where one I/O interface can serve multiple cores concurrently
2Productivity
If the number of chip-level I/Os is increased to access more cores simultaneously, then more cores can be tested concurrently, but routing congestion and design complexity increase
Solution Approach 1:
The patent makes chip-level I/Os universal by enabling them to access multiple different cores through the packet-based interface architecture. Instead of dedicating each I/O to a specific core, the interface devices allow any I/O to dynamically address and access any core by configuring the packet bits appropriately, thus reducing the total number of I/Os needed
Solution Approach 2:
The patent changes the access model from fixed one-to-one I/O-to-core mapping to a flexible packet-based addressing scheme. By changing the parameter of how access is granted (from physical connection to packet routing), the system can achieve higher concurrency with fewer physical I/Os, reducing routing congestion and design complexity
3Ease of manufacture
If static core grouping and connectivity planning is performed early in design, then design dependencies are managed, but sub-optimal results occur due to lack of core-level channel optimization
Solution Approach 1:
The patent introduces dynamic reconfiguration capability through the packet-based access architecture. Instead of static core grouping, the system can dynamically assign different bits in packets to different circuit blocks based on which cores need to be tested concurrently. This dynamic assignment allows optimization of test efficiency while maintaining manageable design planning
Solution Approach 2:
The patent performs preliminary configuration of the packet-based access architecture and interface devices early in design, establishing the flexible access framework. The actual core grouping and bit assignment can then be optimized later based on specific test requirements, allowing both early design planning and late-stage optimization
Data Source
AI summary
Various aspects of the disclosed technology relate to streaming data to circuit blocks in a circuit. A system for streaming data in a circuit comprises a first network comprising first data channels and first interface devices and a second network comprising second data channels and second interface devices. Each of the first interface devices is coupled to ports of one of circuit blocks in the circuit and configurable to transport a plurality of equal-sized data packets consecutively. Each of the second interface devices is coupled to one of the first interface devices and configurable to transport configuration data to the first interface devices. The configuration data comprise data for determining whether or not a first interface device is activated and data for determining which bit or bits of each of the plurality of data packets to be captured, replaced, or captured and replaced by an activated first interface device.