Two-chip Single-die Packet Switch Architecture for DDR SDRAM Latency
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Solution Overview
Problem
The high development costs and complexity of designing single-chip packet switching nodes that support both small and large memory storage requirements due to the need for dual-mode logic and separate addressing schemes for internal and external memory, leading to increased engineering and production costs.
Innovation Solution
A two-chip/single-die packet switch architecture with minimal dual-mode logic, where the packet switch operates in internal memory mode for small embedded SRAM and external memory mode for large DDR SDRAM, using a packet data transfer engine with both internal and external memory mode logic to efficiently manage and transfer data between the two memory types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual-mode logic and separate addressing schemes are implemented to support both small and large memory storage, then memory storage capability is improved, but device complexity and development costs increase
Solution Approach 1:
The packet data transfer engine is designed to perform multiple functions by supporting both internal memory mode and external memory mode operations within a single unified logic structure. The engine can adaptively switch between different memory configurations (small embedded SRAM or large external DDR SDRAM) without requiring separate dual-mode logic paths, thereby achieving versatility while minimizing complexity
Solution Approach 2:
The patent merges the internal memory interface and external memory interface into a single packet data transfer engine that handles both memory types through unified logic. The addressing scheme is also merged into a single unified addressing mechanism that can accommodate both internal and external memory configurations, eliminating the need for separate addressing schemes and reducing overall system complexity
2Adaptability or versatility
If dual-mode logic is implemented to support both internal and external memory modes, then memory storage flexibility is improved, but engineering and production costs increase
Solution Approach 1:
The packet data transfer engine is designed as a universal component that can operate in both internal memory mode and external memory mode, allowing a single chip design to serve multiple market segments (LAN switching with small memory and access switching with large memory) without requiring separate fabrication processes or additional engineering development for different configurations
Solution Approach 2:
The system employs dynamic configuration capability where the packet data transfer engine can adaptively switch between internal and external memory modes based on the specific application requirements. This dynamic adaptability allows the same hardware design to be manufactured once and then configured differently through software or initialization parameters, eliminating the need for costly re-fabrication or additional engineering for different memory configurations
3Quantity of substance
If DDR SDRAM is used for large external memory storage, then memory capacity is improved, but bandwidth utilization efficiency deteriorates
Solution Approach 1:
The packet data transfer engine performs preliminary actions by pre-fetching and buffering data from DDR SDRAM into internal SRAM before packet processing is needed. This preliminary data movement allows the slower external memory to be accessed without bottlenecking the packet processing pipeline, thereby maintaining high bandwidth utilization efficiency while leveraging the large capacity of DDR SDRAM
Solution Approach 2:
The memory system is segmented into two tiers: large-capacity DDR SDRAM for bulk packet storage and high-speed SRAM for active packet processing. The packet data transfer engine manages this segmented architecture by intelligently moving data between tiers, allowing the system to achieve both large memory capacity and high bandwidth utilization by keeping frequently accessed packets in the fast SRAM tier while maintaining capacity in the external DDR SDRAM tier
4Speed
If internal memory store is used for packet storage, then access speed is improved, but memory capacity is limited
Solution Approach 1:
The memory architecture employs a nested structure where small, fast internal SRAM is nested within the larger external DDR SDRAM memory system. The internal SRAM serves as a high-speed cache for actively processed packets, while the external DDR SDRAM provides the larger capacity storage. This nested arrangement allows the system to achieve both high access speed (through the internal SRAM layer) and large memory capacity (through the external DDR SDRAM layer) simultaneously
Data Source
AI summary
A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks. The method relates to a packet data transfer discipline addressing random memory access latencies incurred in employing DDR SDRAM, using predictive bank switching to hide random access latencies, packet length dependent variable memory write burst lengths to minimize bank switching, and performing memory read and write operations during corresponding read and write windows. Advantages are derived from the a space-efficient two-chip/single-die switching node architecture implemented with a reduced amount of dual mode logic, and also from DDR SDRAM bandwidth utilization efficiencies.