Packet Switched Serial Interface for Processor Memory Interconnect
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Solution Overview
Problem
Current computing and communication architectures face limitations in processor-memory interconnect speeds, leading to the 'memory gap' problem, where processor speeds exceed memory access speeds, and serial I/O protocols are inefficient due to high communication overhead and transmission blocking concerns, especially with increasing processor core counts and memory capacities.
Innovation Solution
Implementing a high-speed packet switched serial interface directly on the chip, using a gigabit Ethernet interface with a packet processor co-located with the processor core, to transfer data, address, and control information between processor and memory using a serial packetized protocol, with optional bridge and switch devices for protocol translation and mediation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If parallel bus interconnection (PCI bus) is used for backplane fabric, then standardized interconnection and ease of operation are improved, but communication speed and productivity deteriorate due to inability to match processor speeds
Solution Approach 1:
The patent replaces the traditional parallel bus mechanical interconnection system with a packet-switched serial communication system. Instead of using physical parallel bus lanes (mechanical/electrical connection), the invention uses virtual channel-based packet switching over serial links, enabling speeds that can match processor operations while maintaining standardized interfaces through protocol abstraction.
Solution Approach 2:
The invention changes the fundamental parameters of the interconnection system by transitioning from parallel to serial communication architecture. By using packet switching with virtual channels and protocol translation capabilities, the system achieves higher speeds while maintaining compatibility through parameter transformation rather than physical reconfiguration.
2Speed
If serial I/O protocols are used for communication, then communication speed is improved, but communication overhead and device complexity increase
Solution Approach 1:
The patent introduces protocol translators and switch fabric as intermediary components that mediate between different serial protocols and the packet-switched network. These intermediaries handle protocol conversion, error checking, and flow control, reducing the communication overhead burden on end devices while maintaining high-speed serial communication capabilities.
Solution Approach 2:
The invention creates a universal packet-switched network that can handle multiple protocol types through protocol translators. The switch fabric and virtual channel mechanism provide multi-functional capabilities, allowing a single infrastructure to support various serial protocols (PCI, PCI-X, etc.) without requiring separate dedicated pathways for each protocol.
3Productivity
If processor core count and memory capacity are increased, then computing power and storage are improved, but memory access speed and productivity deteriorate due to memory gap problem
Solution Approach 1:
The patent segments the memory access pathway into multiple independent virtual channels through packet switching. Instead of a single shared memory bus that becomes a bottleneck, the invention divides memory traffic into multiple parallel virtual channels that can be switched independently, allowing multiple processor cores to access memory simultaneously without contending for the same physical resource.
Solution Approach 2:
The invention adds a new dimension to memory access by introducing the packet-switched network layer between processors and memory. This virtual network layer provides an additional pathway for data transfer, transforming the traditional direct bus connection into a multi-dimensional communication space with multiple routes and channels for memory access.
Data Source
AI summary
A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.