Packet Switching Global Synchronization via Autonomous Reference Selection
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Solution Overview
Problem
Existing global synchronization methods in packet switching systems are complex and time-consuming, leading to potential packet loss and congestion when a link or chip malfunctions, especially in large-scale systems with thousands of chips.
Innovation Solution
A hardware-based method where each chip selects a reference chip to calibrate its timer, sending zero-point pulses or cells through high-speed links and feeding back calibration cells, allowing for quick reselection of a new reference when necessary, thereby reducing packet loss and improving calibration accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a software-based reference selection method is used where the network manager collects chip states and issues commands to designate a reference chip, then the system can determine which chip should be the reference, but the process becomes complicated and time-consuming, especially in large-scale systems with thousands of chips
Solution Approach 1:
Each chip autonomously selects its reference chip based on pre-stored reference chip information without requiring centralized software management. When a chip detects that its reference is unavailable, it automatically selects a new reference from its stored list, eliminating the need for network manager intervention and significantly reducing reselection time.
Solution Approach 2:
Reference chip information is pre-stored in each chip's memory during system initialization or manufacturing. This preliminary preparation ensures that when a reference failure occurs, the chip can immediately select from pre-validated reference candidates without waiting for software-based determination, thus reducing packet loss and congestion.
2Adaptability or versatility
If software-based reference selection and command issuance is performed for each chip, then the system can adapt to link or chip failures, but the state collection and command issuing process is long, leading to packet loss or congestion
Solution Approach 1:
Each chip independently monitors its own reference status and autonomously performs reference reselection when needed. This self-service mechanism eliminates the slow software-based state collection and command issuance process, enabling rapid adaptation to failures while maintaining high synchronization speed across the system.
Solution Approach 2:
The reference selection function is segmented and distributed to individual chips rather than being centralized in software. Each chip maintains its own reference information and makes independent selection decisions, allowing parallel reference reselection across multiple chips simultaneously, thus dramatically improving system-wide synchronization speed.
3Loss of time
If a hardware-based operation is used for reference reselection and synchronization, then the process can be completed in short time, but the system requires pure-hardware implementation which may increase device complexity
Solution Approach 1:
The software-based reference selection process is replaced with a hardware-based autonomous selection mechanism. Each chip contains hardware logic that automatically monitors reference status and performs reselection based on pre-stored information, eliminating the need for software intervention and achieving rapid reference reselection through hardware-level operations.
Solution Approach 2:
The hardware implementation enables each chip to autonomously manage its own reference selection without external control. The chip's internal hardware circuits automatically detect reference failures and select new references from pre-stored candidates, reducing reselection time while the modular hardware design keeps implementation complexity manageable.
Data Source
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AI summary
A global synchronization method based on a packet switching system includes that: a reference chip is selected; and each chip calibrates its own timer by taking the reference chip as a reference, wherein each chip sends a zero-point pulse or zero-point pulse cell to each high-speed link (serdes) connected with the chip, and feeds back a calibration cell in response to a zero-point pulse or zero-point pulse cell received through each high-speed link. Accordingly, a global synchronization system based on a packet switching system is also disclosed. The disclosure reduces the packet loss rate and increases the accuracy of calibration.