Packet Timeout Detection Logic Using Shared Counter and FIFO
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Solution Overview
Problem
Existing packet-switched point-to-point communication systems, such as RAPIDIO, require significant programmable resources to detect timeouts for packets, which is inefficient and resource-intensive, especially in FPGA implementations.
Innovation Solution
A method and apparatus utilizing a master time counter, FIFO, difference logic, timeout counter, and timeout detection logic to efficiently detect packet timeouts with minimal logic resources, including a first-in-first-out circuit for storing time stamps and computing a time left value, and generating a timeout signal when the counter reaches zero.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If 32 large counters are employed to track each outstanding packet individually, then packet timeout detection accuracy is improved, but the number of registers and logic resources increases significantly
Solution Approach 1:
The patent merges the timeout tracking function into a single counter that shares the FIFO structure with packet transmission tracking. Instead of having separate counters for each packet, the system uses one counter that is incremented when packets are transmitted and decremented when acknowledged, thereby detecting timeouts indirectly. This consolidation dramatically reduces the number of registers from 928 to a minimal amount while maintaining detection accuracy.
Solution Approach 2:
The single counter serves multiple functions: it tracks the number of outstanding packets, determines when packets are acknowledged, and detects timeout conditions. By making the counter universal for these different purposes, the patent eliminates the need for separate dedicated counters for each function, thus reducing overall logic resource consumption while preserving all necessary detection capabilities.
2Reliability
If a register implementation of counters is used for each outstanding packet, then timeout detection capability is improved, but the consumption of programmable resources increases
Solution Approach 1:
The patent combines multiple timeout detection functions into a single counter implementation that operates alongside the packet transmission counter. This unified approach allows the system to detect timeouts for multiple packets using one counter resource instead of requiring separate register implementations for each packet, thereby reducing programmable resource consumption while maintaining reliable timeout detection.
Solution Approach 2:
The single counter automatically performs multiple functions including tracking outstanding packets, detecting acknowledgments, and identifying timeouts without requiring separate dedicated resources for each function. The counter serves itself by using its own state changes to trigger different operations (packet transmission, acknowledgment processing, timeout detection), thereby eliminating the need for additional programmable resources.
Data Source
AI summary
Method and apparatus for detecting timeout for packets transmitted in a packet-switched point-to-point communication system is described. In one example, timeout logic in a transmitter includes a master time counter, a first-in-first-out circuit (FIFO), difference logic, a timeout counter, and timeout detection logic. The master time counter generates a time signal, and the FIFO stores time stamps for the packets in response to the time signal. The FIFO provides a time stamp to the difference logic in response to a packet acknowledgement. The difference logic computes a time left value in response to the time stamp, the time signal, and a predefined timeout value. The timeout counter counts down from the time left value towards a zero value. The timeout detection logic produces a timeout signal in response to the timeout counter reaching the zero value.