Packet Timestamp Correction for FEC-Induced Network Latency

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Solution Overview

Problem

Conventional Ethernet network systems fail to accurately account for latency changes associated with enabling or disabling Forward Error Correction (FEC) decoding, leading to imprecise clock synchronization, which is critical for applications requiring precise timing.

Innovation Solution

The network system includes a time stamp module that adjusts packet timestamps with correction factors based on the current FEC decoding mode, accounting for delays caused by FEC processing, allowing for accurate synchronization between network nodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If FEC decoding is enabled to improve packet integrity on marginal channels, then reliability is improved, but latency increases and system performance degrades

Engineering Contradiction:
Improvepacket integrityVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system dynamically adjusts the FEC decoding mode based on real-time channel quality measurements. The receiver monitors channel conditions and switches between different FEC decoding modes (e.g., mode A and mode B with different latency characteristics) to optimize the balance between packet integrity and latency under varying network conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the operational parameters of the FEC decoder by selecting different decoding modes with distinct latency characteristics. When channel quality is good, the system uses a lower-latency mode; when channel quality degrades, it switches to a more robust but higher-latency mode, thereby adapting the latency parameter to match reliability requirements.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If FEC decoding mode is changed to adapt to channel quality, then reliability is optimized, but clock synchronization precision deteriorates due to unaccounted latency changes

Engineering Contradiction:
Improvepacket integrityVSAvoidclock synchronization precision
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The system implements feedback mechanisms where the receiver communicates FEC mode information and channel quality status to the transmitter. This feedback loop enables both ends to synchronize their clock adjustments based on actual FEC operation status, ensuring that latency corrections applied during synchronization reflect the true operational state of the FEC decoder.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system performs preliminary measurements and calculations of latency variations associated with different FEC modes before actual data transmission occurs. These pre-characterized latency values are stored and applied during clock synchronization, allowing the system to anticipate and compensate for FEC-induced latency changes without waiting for actual packet processing to complete.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If FEC decoder is left on continuously to ensure packet integrity, then reliability is maintained, but power demand increases

Engineering Contradiction:
Improvepacket integrityVSAvoidpower demand
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

Instead of continuously operating the FEC decoder at full capacity, the system employs periodic action by switching between active FEC decoding and reduced-activity states based on channel quality. During periods of good channel conditions, the FEC decoder operates in a low-power mode or is temporarily disabled, while activating full FEC processing only when channel degradation is detected, thereby reducing average power consumption while maintaining reliability.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8826103B2Time protocol latency correction based on forward error correction status
Publication Date: 2014.09.02 INTEL CORP
  • US8826103B2 patent drawing
  • US8826103B2 patent drawing
  • US8826103B2 patent drawing

AI summary

One embodiment provides a method for time protocol latency correction based on forward error correction (FEC) status. The method includes determining, by a network node element, if a forward error correction (FEC) decoding mode is enabled or disabled for a packet received from a link partner in communication with the network node element. The method also includes determining, by the network node element, a first time correction factor if an FEC decoding mode is enabled, the first time correction factor includes a time delay associated with the enabled FEC decoding mode and the first time correction factor is applied to a time stamp associated with the packet. The method also includes determining, by the network node element, a second time correction factor if an FEC decoding mode is disabled, the second time correction factor is applied to the time stamp associated with the packet.